migrate jelib->delib

[fleet.git] / chips / marina / electric / wiresL.delib / pinsVddGnd.lay

diff --git a/chips/marina/electric/wiresL.delib/pinsVddGnd.lay b/chips/marina/electric/wiresL.delib/pinsVddGnd.lay
new file mode 100644 (file)
index 0000000..4370b85
--- /dev/null
+++ b/chips/marina/electric/wiresL.delib/pinsVddGnd.lay
@@ -0,0 +1,12 @@
+HwiresL|8.10k
+
+# Cell pinsVddGnd;1{lay}
+CpinsVddGnd;1{lay}||cmos90|1180462114023|1241981698008|I|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1242253744604|FACET_characteristic_spacing()D[0.0,144.0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NMetal-2-Pin|pin@0||0|50|||Y|
+NMetal-2-Pin|pin@1||0|0|||Y|
+NMetal-2-Pin|pin@2||0|-50|||Y|
+Egnd||D5G2;|pin@1||G
+Evdd||D5G2;|pin@0||P
+Evdd_1||D5G2;|pin@2||P
+X