migrate jelib->delib

[fleet.git] / chips / marina / electric / wiresL.delib / select90.lay

diff --git a/chips/marina/electric/wiresL.delib/select90.lay b/chips/marina/electric/wiresL.delib/select90.lay
new file mode 100644 (file)
index 0000000..87fa2e0
--- /dev/null
+++ b/chips/marina/electric/wiresL.delib/select90.lay
@@ -0,0 +1,12 @@
+HwiresL|8.10k
+
+# Cell select90;1{lay}
+Cselect90;1{lay}||cmos90|1180136751346|1241981698008|I|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981751253
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NP-Well-Node|plnode@0||0|0|90|48||A
+NN-Well-Node|plnode@1||0|-50|90|52||A
+NN-Well-Node|plnode@2||0|50|90|52||A
+NP-Select-Node|plnode@3||0|-50|87|52||A
+NP-Select-Node|plnode@4||0|50|87|52||A
+NN-Select-Node|plnode@5||0|0|87|48||A
+X