migrate jelib->delib

[fleet.git] / chips / marina / electric / wiresL.delib / tranCap.lay

diff --git a/chips/marina/electric/wiresL.delib/tranCap.lay b/chips/marina/electric/wiresL.delib/tranCap.lay
new file mode 100644 (file)
index 0000000..a5d4f46
--- /dev/null
+++ b/chips/marina/electric/wiresL.delib/tranCap.lay
@@ -0,0 +1,412 @@
+HwiresL|8.10k
+
+# Cell tranCap;1{lay}
+CtranCap;1{lay}||cmos90|1238423100662|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981751253
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