migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / omegaCounter-old.delib / buf.sch

diff --git a/chips/omegaCounter/40nm/electric/omegaCounter-old.delib/buf.sch b/chips/omegaCounter/40nm/electric/omegaCounter-old.delib/buf.sch
new file mode 100644 (file)
index 0000000..93ccb82
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/omegaCounter-old.delib/buf.sch
@@ -0,0 +1,23 @@
+HomegaCounter-old|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell buf;2{sch}
+Cbuf;2{sch}||schematic|1021415734000|1253487811856||ATTR_Delay(D5G1;HNPX-12;Y-5.5;)I100|ATTR_LEGATE(D5G1;HNPTX-12;Y-10.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-12;Y-6.5;)I-1|ATTR_X(D5G1;HNOJPX-12.5;Y-4.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-12;Y-7.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-8.5;)Sstrong1|ATTR_su(D5G1;HNPTX-12;Y-9.5;)I-1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||11|0||||
+NOff-Page|conn@1||-14|0||||
+Ibuf;1{ic}|inv@1||20|13.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)S""
+IredFive:inv;1{ic}|inv@2||-4.5|0|||D5G4;|ATTR_X(D5FLeave alone;G1.5;NOLPX1.5;Y3.5;)S@X|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@0||2|0|||D5G4;|ATTR_X(D5FLeave alone;G1.5;NOLPX1.25;Y3.5;)S@X|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Ngeneric:Invisible-Pin|pin@1||11|-12|||||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
+Ngeneric:Invisible-Pin|pin@2||-1.5|14.5|||||ART_message(D5G2;)S[a pair of inverters,"sized to have \"one gate delay\""]
+Ngeneric:Invisible-Pin|pin@3||-1.5|20|||||ART_message(D5G6;)Sbuf
+Awire|net@4|||0|invI@0|in|-0.5|0|inv@2|out|-2|0
+Awire|net@5|||1800|invI@0|out|4.5|0|conn@0|a|9|0
+Awire|net@6|||0|inv@2|in|-7|0|conn@1|y|-12|0
+Ein||D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)S.25
+Eout||D5G2;|conn@0|y|O|ATTR_le(D5G1;NY2;)I1
+X