migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / omegaCounter-old.delib / fakeForDRC.lay

diff --git a/chips/omegaCounter/40nm/electric/omegaCounter-old.delib/fakeForDRC.lay b/chips/omegaCounter/40nm/electric/omegaCounter-old.delib/fakeForDRC.lay
new file mode 100644 (file)
index 0000000..c91a9e6
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/omegaCounter-old.delib/fakeForDRC.lay
@@ -0,0 +1,59 @@
+HomegaCounter-old|8.10k
+
+# Cell fakeForDRC;1{lay}
+CfakeForDRC;1{lay}|oneCell|tsmcSun40GP|1250309607249|1250370709293||ATTR_NCC(D5G10;NTX-360;Y618.75;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/","exportsConnectedByParent disableLO /disableLO_[0-9]+/","exportsConnectedByParent disable /disable_[0-9]+/"]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+IoneCell;1{lay}|oneCell@0||1.5|-164.5|R||D5G4;
+ELSN[OneOrDone]||D5G2;|oneCell@0|LSN[OneOrDone]|B
+ELSN[OneOrTwo]||D5G2;|oneCell@0|LSN[OneOrTwo]|B
+EMSN[OneOrDone]||D5G2;|oneCell@0|MSN[OneOrDone]|B
+EMSN[OneOrTwo]||D5G2;|oneCell@0|MSN[OneOrTwo]|B
+Egnd||D5G2;|oneCell@0|gnd|G
+Egnd_1||D5G2;|oneCell@0|gnd_1|G
+Egnd_2||D5G2;|oneCell@0|gnd_2|G
+Egnd_3||D5G2;|oneCell@0|gnd_3|G
+Egnd_4||D5G2;|oneCell@0|gnd_4|G
+Egnd_5||D5G2;|oneCell@0|gnd_5|G
+Egnd_6||D5G2;|oneCell@0|gnd_6|G
+Egnd_16||D5G2;|oneCell@0|gnd_16|U
+Egnd_17||D5G2;|oneCell@0|gnd_17|U
+Egnd_18||D5G2;|oneCell@0|gnd_18|U
+Egnd_19||D5G2;|oneCell@0|gnd_19|U
+Egnd_21||D5G2;|oneCell@0|gnd_21|U
+Egnd_22||D5G2;|oneCell@0|gnd_22|U
+Egnd_24||D5G2;|oneCell@0|gnd_24|U
+Egnd_28||D5G2;|oneCell@0|gnd_28|U
+Egnd_29||D5G2;|oneCell@0|gnd_29|G
+Egnd_30||D5G2;|oneCell@0|gnd_30|G
+Egnd_31||D5G2;|oneCell@0|gnd_31|G
+Eload||D5G2;|oneCell@0|load|I
+EloadLO||D5G2;|oneCell@0|loadLO|I
+EloadLO_1||D5G2;|oneCell@0|disableLO_5|I
+EloadLO_2||D5G2;|oneCell@0|disableLO_2|I
+EloadLO_3||D5G2;|oneCell@0|loadLO_3|I
+EloadLO_4||D5G2;|oneCell@0|loadLO_4|I
+Eload_1||D5G2;|oneCell@0|disable_2|I
+Eload_2||D5G2;|oneCell@0|disable_3|I
+Eload_3||D5G2;|oneCell@0|disable_1|I
+Eload_4||D5G2;|oneCell@0|load_4|I
+Es[1]||D5G2;|oneCell@0|s[1]|O
+Es[2]||D5G2;|oneCell@0|s[2]|O
+EvalLO||D5G2;|oneCell@0|valLO|I
+Evdd||D5G2;|oneCell@0|vdd|P
+Evdd_1||D5G2;|oneCell@0|vdd_1|P
+Evdd_2||D5G2;|oneCell@0|vdd_2|P
+Evdd_3||D5G2;|oneCell@0|vdd_3|P
+Evdd_4||D5G2;|oneCell@0|vdd_4|P
+Evdd_5||D5G2;|oneCell@0|vdd_5|P
+Evdd_6||D5G2;|oneCell@0|vdd_6|P
+Evdd_10||D5G2;|oneCell@0|vdd_10|U
+Evdd_11||D5G2;|oneCell@0|vdd_11|U
+Evdd_12||D5G2;|oneCell@0|vdd_12|U
+Evdd_13||D5G2;|oneCell@0|vdd_13|U
+Evdd_14||D5G2;|oneCell@0|vdd_14|U
+Evdd_16||D5G2;|oneCell@0|vdd_16|U
+Evdd_17||D5G2;|oneCell@0|vdd_17|U
+Evdd_25||D5G2;|oneCell@0|vdd_25|P
+Evdd_26||D5G2;|oneCell@0|vdd_26|P
+Evdd_27||D5G2;|oneCell@0|vdd_27|P
+X