migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / omegaCounter.delib / newCell.ic

diff --git a/chips/omegaCounter/40nm/electric/omegaCounter.delib/newCell.ic b/chips/omegaCounter/40nm/electric/omegaCounter.delib/newCell.ic
new file mode 100644 (file)
index 0000000..3ae9a48
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/omegaCounter.delib/newCell.ic
@@ -0,0 +1,46 @@
+HomegaCounter|8.10k
+
+# Cell newCell;1{ic}
+CnewCell;1{ic}||artwork|1242937501096|1254097696209|E
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NTriangle|art@2||3|6.5|3|2|R|
+NTriangle|art@3||3|-8|3|2|R|
+NTriangle|art@4||-5|6.5|3|2|RRR|
+NPin|pin@0||-6|8.5|1|1||
+NPin|pin@1||-6|-10|1|1||
+NPin|pin@2||4|-10|1|1||
+NPin|pin@3||4|8.5|1|1||
+Nschematic:Wire_Pin|pin@9||-6|-7.5||||
+Nschematic:Wire_Pin|pin@16||4|-8.5||||
+Nschematic:Wire_Pin|pin@17||4|6||||
+Nschematic:Wire_Pin|pin@18||-6|6||||
+NPin|pin@20||-6|6|1|1||
+NPin|pin@33||-6|-7.5|1|1||
+Nschematic:Bus_Pin|pin@38||-3.5|-10||||
+Nschematic:Wire_Pin|pin@39||-3.5|-10||||
+Ngeneric:Invisible-Pin|pin@40||-1|-0.5|||||ART_message(D5G2;)S[Counter,GasP,Module]
+Nschematic:Bus_Pin|pin@41||1.5|-10||||
+Nschematic:Wire_Pin|pin@42||2|-10||||
+Nschematic:Bus_Pin|pin@43||-1|-10||||
+Nschematic:Wire_Pin|pin@44||0.5|-10||||
+Nschematic:Bus_Pin|pin@45||0|8.5||||
+Nschematic:Wire_Pin|pin@46||0|-7||||
+Nschematic:Bus_Pin|pin@47||4|9||||
+ASolid|net@0|||FS900|pin@0||-6|8.5|pin@1||-6|-10
+ASolid|net@1|||FS1800|pin@1||-6|-10|pin@2||4|-10
+ASolid|net@2|||FS2700|pin@2||4|-10|pin@3||4|8.5
+ASolid|net@3|||FS0|pin@3||4|8.5|pin@0||-6|8.5
+Aschematic:wire|net@12|||2700|pin@39||-3.5|-10|pin@38||-3.5|-10
+Aschematic:wire|net@13|||0|pin@42||2|-10|pin@41||1.5|-10
+Aschematic:wire|net@14|||0|pin@44||0.5|-10|pin@43||-1|-10
+Aschematic:wire|net@15|||2700|pin@46||0|-7|pin@45||0|8.5
+ELSN[OneOrTwo]|LSN[TwoOrDone]|D5G1;X5;|pin@17||B
+ELSN[OneOrDone]|LSN[TwoOrOne]|D6G1;X1;|pin@16||B
+EMSN[OneOrTwo]|MSN[TwoOrDone]|D4G1;X-1;|pin@18||B
+EMSN[OneOrDone]|MSN[TwoOrOne]|D4G1;X-1;|pin@9||B
+Edisable||D5G2;X6;Y-1;|pin@41||I
+EdisableLO||D5G2;X-6.5;Y-1;|pin@38||I
+EdisableLO_1@406729688|disableLate|D5G2;|pin@45||I
+Evdd_when_not_disabled|highWhenNotDisabled|D5G2;|pin@47||I
+EdisableLO_1|valLO|D5G2;|pin@43||I
+X