migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / orange40nm.delib / PMOSf_low.sch

diff --git a/chips/omegaCounter/40nm/electric/orange40nm.delib/PMOSf_low.sch b/chips/omegaCounter/40nm/electric/orange40nm.delib/PMOSf_low.sch
new file mode 100644 (file)
index 0000000..949e3dd
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/orange40nm.delib/PMOSf_low.sch
@@ -0,0 +1,25 @@
+Horange40nm|8.10k
+
+# Cell PMOSf_low;1{sch}
+CPMOSf_low;1{sch}||schematic|1021415734000|1245267494503||ATTR_Delay(D5G1;HNPTX-7;Y0.75;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX-7;Y3;)S4|ATTR_M1(D5G1;HNOLPX-7;Y-1;)S1|ATTR_NF(D5G1;HNOLPX-7;Y2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-7;Y4;)S19.5|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SXM$(node_name) $(d) $(g) $(s) vdd pch_lvt_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_low;1{ic}|PMOSf_lo@0||30.5|19|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S19.5
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)SPMOSf_low
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S3-terminal low threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_M(D5G1;NOLX-2.5;Y-4;)S@M1|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch_lvt
+NPower|pwr@0||6|8||||
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X