merge omegaCounter 40nm/90nm branches into chips/omegaCounter/

[fleet.git] / chips / omegaCounter / 40nm / electric / orange40nm.jelib

diff --git a/chips/omegaCounter/40nm/electric/orange40nm.jelib b/chips/omegaCounter/40nm/electric/orange40nm.jelib
new file mode 100644 (file)
index 0000000..bd8c817
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/orange40nm.jelib
@@ -0,0 +1,1577 @@
+# header information:
+Horange40nm|8.10a
+
+# Views:
+Vicon|ic
+Vschematic|sch
+
+# Tools:
+Ouser|DefaultTechnology()Scmos90|SchematicTechnology()Scmos90
+Oio|GDSOutputConvertsBracketsInExports()BF|GDSWritesExportPins()BT
+OGateLayoutGenerator|enableNCC()SPurpleFour
+OSTA|GlobalSDCCommands()S"\n### 4 GHz clock setup\ncreate_clock -period 0.250 -name clk -waveform \"0 0.125\" clk\nset_clock_uncertainty -setup 0.010 clk\nset_clock_uncertainty -hold 0.010 clk\nset_propagated_clock clk\nset_clock_transition -rise 0.030 clk\nset_clock_transition -fall 0.030 clk\n#set_driving_cell -lib_cell inv_X008_0 clk\n\n### remove scan path from timing\nset_false_path -through */so\nset_false_path -through */*/so\nset_false_path -through */*/*/so\nset_false_path -through */*/*/*/so\nset_false_path -from {sin}\nset_false_path -from {scanEn}\nset_false_path -to {sout}\n"
+
+# Technologies:
+Tartwork|SelectedFoundryForartwork()S""
+Tcmos90|"GDS(TSMC)LayerForOD33INcmos90"()S111
+Ttft|SelectedFoundryFortft()SMOSIS
+
+# Cell NMOS4f;1{ic}
+CNMOS4f;1{ic}||artwork|1021415734000|1241210880338|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S4|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S15|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.5|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1.5|1|1|1||
+NPin|pin@7||-1.5|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Nschematic:Bus_Pin|pin@13||0|-0.5|-2|-2||
+NPin|pin@15||-0.25|-0.75||||
+NPin|pin@16||-0.25|-0.25||||
+NPin|pin@17||-0.75|-0.5|1|1|RR|
+NPin|pin@18||0|-0.5|||RR|
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1.5|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-1.5|1|pin@7||-1.5|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+AThicker|net@8|||FS2250|pin@15||-0.25|-0.75|pin@18||0|-0.5|ART_color()I74
+AThicker|net@9|||FS1350|pin@16||-0.25|-0.25|pin@18||0|-0.5|ART_color()I74
+AThicker|net@10|||FS1800|pin@17||-0.75|-0.5|pin@18||0|-0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4f;1{sch}
+CNMOS4f;1{sch}||schematic|1021415734000|1243981113049||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S4|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S15|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) $(b) nch_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f;1{ic}|NMOS4f@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S4|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S15
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NOff-Page|conn@3||5.5|-9||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)SNMOS4f
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S4-terminal standard threshold NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@6|||0|conn@3|a|3.5|-9|nmos4p@0|b|0|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOS4f_dnw;1{ic}
+CNMOS4f_dnw;1{ic}||artwork|1021415734000|1244675981257|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S4|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S15|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.5|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1.5|1|1|1||
+NPin|pin@7||-1.5|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Nschematic:Bus_Pin|pin@13||0|-0.5|-2|-2||
+NPin|pin@15||-0.25|-0.75||||
+NPin|pin@16||-0.25|-0.25||||
+NPin|pin@17||-0.75|-0.5|1|1|RR|
+NPin|pin@18||0|-0.5|||RR|
+Ngeneric:Invisible-Pin|pin@19||0.5|0.5|||||ART_message(BC106;D5G1;)Sdnw
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1.5|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-1.5|1|pin@7||-1.5|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+AThicker|net@8|||FS2250|pin@15||-0.25|-0.75|pin@18||0|-0.5|ART_color()I74
+AThicker|net@9|||FS1350|pin@16||-0.25|-0.25|pin@18||0|-0.5|ART_color()I74
+AThicker|net@10|||FS1800|pin@17||-0.75|-0.5|pin@18||0|-0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4f_dnw;1{sch}
+CNMOS4f_dnw;1{sch}||schematic|1021415734000|1244676270446||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S4|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S15|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) $(b) nch_dnw W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) $(b) nch_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) $(b) nch_dnw W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_dnw;1{ic}|NMOS4f_d@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S4|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S15
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NOff-Page|conn@3||5.5|-9||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)SNMOS4f_dnw
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S4-terminal standard threshold deep nwell NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@6|||0|conn@3|a|3.5|-9|nmos4p@0|b|0|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOS4f_high;1{ic}
+CNMOS4f_high;1{ic}||artwork|1021415734000|1245267258273|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S4|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S15|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Nschematic:Bus_Pin|pin@13||0|-0.5|-2|-2||
+NPin|pin@15||-0.25|-0.75||||
+NPin|pin@16||-0.25|-0.25||||
+NPin|pin@17||-0.75|-0.5|1|1|RR|
+NPin|pin@18||0|-0.5|||RR|
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-2|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+AThicker|net@8|||FS2250|pin@15||-0.25|-0.75|pin@18||0|-0.5|ART_color()I74
+AThicker|net@9|||FS1350|pin@16||-0.25|-0.25|pin@18||0|-0.5|ART_color()I74
+AThicker|net@10|||FS1800|pin@17||-0.75|-0.5|pin@18||0|-0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4f_high;1{sch}
+CNMOS4f_high;1{sch}||schematic|1021415734000|1245267253761||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S4|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S15|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) $(b) nch_hvt_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_high;1{ic}|NMOS4f_h@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S4|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S15
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NOff-Page|conn@3||5.5|-9||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_hvt
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)SNMOS4f_high
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S4-terminal high threshold NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@6|||0|conn@3|a|3.5|-9|nmos4p@0|b|0|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOS4f_io18;1{ic}
+CNMOS4f_io18;1{ic}||artwork|1021415734000|1244051425806|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S15|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S32|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Nschematic:Bus_Pin|pin@13||0|-0.5|-2|-2||
+NPin|pin@15||-0.25|-0.75||||
+NPin|pin@16||-0.25|-0.25||||
+NPin|pin@17||-0.75|-0.5|1|1|RR|
+NPin|pin@18||0|-0.5|||RR|
+Ngeneric:Invisible-Pin|pin@19||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3.5|0|pin@1||-2|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+AThicker|net@8|||FS2250|pin@15||-0.25|-0.75|pin@18||0|-0.5|ART_color()I74
+AThicker|net@9|||FS1350|pin@16||-0.25|-0.25|pin@18||0|-0.5|ART_color()I74
+AThicker|net@10|||FS1800|pin@17||-0.75|-0.5|pin@18||0|-0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4f_io18;1{sch}
+CNMOS4f_io18;1{sch}||schematic|1021415734000|1245272156473||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S15|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S32|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) $(b) nch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) $(b) nch_18_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) $(b) nch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_18 W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_io18;1{ic}|NMOS4f_i@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S15|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S32
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NOff-Page|conn@3||5.5|-9||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_18
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|18|||||ART_message(D5G6;)SNMOS4f_io18
+Ngeneric:Invisible-Pin|pin@3||1.5|11.5|||||ART_message(D5G2;)S4-terminal NMOS device for 1.8V I/O pads
+Ngeneric:Invisible-Pin|pin@4||2.5|8|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 15 (0.15um)
+Ngeneric:Invisible-Pin|pin@5||1|6|||||ART_message(D5G2;)Sminimum width is 32 (0.32um)
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@6|||0|conn@3|a|3.5|-9|nmos4p@0|b|0|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOS4f_low;1{ic}
+CNMOS4f_low;1{ic}||artwork|1021415734000|1245267035055|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S4|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S15|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1|1|1|1||
+NPin|pin@7||-1|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Nschematic:Bus_Pin|pin@13||0|-0.5|-2|-2||
+NPin|pin@15||-0.25|-0.75||||
+NPin|pin@16||-0.25|-0.25||||
+NPin|pin@17||-0.75|-0.5|1|1|RR|
+NPin|pin@18||0|-0.5|||RR|
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-1|1|pin@7||-1|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+AThicker|net@8|||FS2250|pin@15||-0.25|-0.75|pin@18||0|-0.5|ART_color()I74
+AThicker|net@9|||FS1350|pin@16||-0.25|-0.25|pin@18||0|-0.5|ART_color()I74
+AThicker|net@10|||FS1800|pin@17||-0.75|-0.5|pin@18||0|-0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4f_low;1{sch}
+CNMOS4f_low;1{sch}||schematic|1021415734000|1245267028797||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S4|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S15|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) $(b) nch_lvt_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_low;1{ic}|NMOS4f_l@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S4|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S15
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NOff-Page|conn@3||5.5|-9||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_lvt
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)SNMOS4f_low
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S4-terminal low threshold NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@6|||0|conn@3|a|3.5|-9|nmos4p@0|b|0|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOS4f_native;1{ic}
+CNMOS4f_native;1{ic}||artwork|1021415734000|1241331284383|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S30|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S15|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-0.75|0|1|1|RR|
+NPin|pin@2||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Nschematic:Bus_Pin|pin@13||0|-0.5|-2|-2||
+NPin|pin@15||-0.25|-0.75||||
+NPin|pin@16||-0.25|-0.25||||
+NPin|pin@17||-0.75|-0.5|1|1|RR|
+NPin|pin@18||0|-0.5|||RR|
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-2.5|0|pin@1||-0.75|0|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+AThicker|net@8|||FS2250|pin@15||-0.25|-0.75|pin@18||0|-0.5|ART_color()I74
+AThicker|net@9|||FS1350|pin@16||-0.25|-0.25|pin@18||0|-0.5|ART_color()I74
+AThicker|net@10|||FS1800|pin@17||-0.75|-0.5|pin@18||0|-0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4f_native;1{sch}
+CNMOS4f_native;1{sch}||schematic|1021415734000|1245272183894||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S30|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S15|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) $(b) nch_na_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_native;1{ic}|NMOS4f_n@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S30|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S15
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NOff-Page|conn@3||5.5|-9||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_na
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|17|||||ART_message(D5G6;)SNMOS4f_native
+Ngeneric:Invisible-Pin|pin@3||1.5|10.5|||||ART_message(D5G2;)S4-terminal native NMOS device
+Ngeneric:Invisible-Pin|pin@4||3.5|6.5|||||ART_message(D5G2;)Sminimum length for native devices is 30 (0.30um)
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@6|||0|conn@3|a|3.5|-9|nmos4p@0|b|0|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf;1{ic}
+CNMOSf;1{ic}||artwork|1021415734000|1241200531652|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S4|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S15|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.5|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1.5|1|1|1||
+NPin|pin@7||-1.5|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1.5|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-1.5|1|pin@7||-1.5|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf;1{sch}
+CNMOSf;1{sch}||schematic|1021415734000|1243980877666||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S4|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S15|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) gnd nch_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf;1{ic}|NMOSf@1||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S15
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX0.5;Y-4;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)S[NMOSf]
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S3-terminal standard threshold NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_high;1{ic}
+CNMOSf_high;1{ic}||artwork|1021415734000|1245267168676|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S4|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S15|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-2|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_high;1{sch}
+CNMOSf_high;1{sch}||schematic|1021415734000|1245267219413||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S4|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S15|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) gnd nch_hvt_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_high;1{ic}|NMOSf_hi@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S15
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX0.5;Y-4;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_hvt
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)SNMOSf_high
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S3-terminal high threshold NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_io18;1{ic}
+CNMOSf_io18;1{ic}||artwork|1021415734000|1244051380936|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S15|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S32|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3.5|0|pin@1||-2|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_io18;1{sch}
+CNMOSf_io18;1{sch}||schematic|1021415734000|1245272160722||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S15|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S32|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) gnd nch_18_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_io18;1{ic}|NMOSf_io@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S15|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S32
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX0.5;Y-4;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_18
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|18|||||ART_message(D5G6;)SNMOSf_io18
+Ngeneric:Invisible-Pin|pin@3||1.5|11.5|||||ART_message(D5G2;)S3-terminal NMOS device for 1.8V I/O pads
+Ngeneric:Invisible-Pin|pin@4||3|8|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 15 (0.15um)
+Ngeneric:Invisible-Pin|pin@5||3|6|||||ART_message(D5G2;)Sminimum width is 32 (0.32um)
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_low;1{ic}
+CNMOSf_low;1{ic}||artwork|1021415734000|1245266962978|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S4|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S15|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1|1|1|1||
+NPin|pin@7||-1|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-1|1|pin@7||-1|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_low;1{sch}
+CNMOSf_low;1{sch}||schematic|1021415734000|1245266949165||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S4|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S15|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) gnd nch_lvt_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_low;1{ic}|NMOSf_lo@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S15
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX0.5;Y-4;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_lvt
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)SNMOSf_low
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S3-terminal low threshold NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_native;1{ic}
+CNMOSf_native;1{ic}||artwork|1021415734000|1241330691667|E|ATTR_Delay(D5G1;HNPTX3;Y-2;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX2;Y1;)S30|ATTR_M1(D5G1;HNOLPX2;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2;Y2;)S15|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-0.75|0|1|1|RR|
+NPin|pin@2||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-2.5|0|pin@1||-0.75|0|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_native;1{sch}
+CNMOSf_native;1{sch}||schematic|1021415734000|1245272179253||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S30|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S15|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) gnd nch_na_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_native;1{ic}|NMOSf_na@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S30|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S15
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_na
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|16|||||ART_message(D5G6;)SNMOSf_native
+Ngeneric:Invisible-Pin|pin@3||1.5|9.5|||||ART_message(D5G2;)S3-terminal native NMOS device
+Ngeneric:Invisible-Pin|pin@4||3|6|||||ART_message(D5G2;)Sminimum length for native devices is 30 (0.30um)
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f;1{ic}
+CPMOS4f;1{ic}||artwork|1021415734000|1241211040052|E|ATTR_Delay(D5G1;HNPTX2.5;Y-2;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX2.5;Y1;)S4|ATTR_M1(D5G1;HNOLPX2.5;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2.5;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2.5;Y2;)S19.5|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3|0|||RR|
+NPin|pin@9||-2.5|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-1.5|1|1|1|Y|
+NPin|pin@12||-1.5|-1|1|1|Y|
+Nschematic:Bus_Pin|pin@13||0|0.5|-2|-2||
+NPin|pin@15||-0.5|0.25|1|1|YRR|
+NPin|pin@16||-0.5|0.75|1|1|YRR|
+NPin|pin@17||-0.75|0.5|1|1|Y|
+NPin|pin@18||0|0.5||||
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3|0|pin@9||-2.5|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-1.5|-1|pin@11||-1.5|1|ART_color()I74
+AThicker|net@8|||FS3150|pin@15||-0.5|0.25|pin@17||-0.75|0.5|ART_color()I74
+AThicker|net@9|||FS450|pin@16||-0.5|0.75|pin@17||-0.75|0.5|ART_color()I74
+AThicker|net@10|||FS0|pin@18||0|0.5|pin@17||-0.75|0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOS4f;1{sch}
+CPMOS4f;1{sch}||schematic|1021415734000|1243981194994||ATTR_Delay(D5G1;HNPTX-7;Y0.75;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX-7;Y3;)S4|ATTR_M1(D5G1;HNOLPX-7;Y-1;)S1|ATTR_NF(D5G1;HNOLPX-7;Y2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-7;Y4;)S19.5|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SXM$(node_name) $(d) $(g) $(s) $(b) pch_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f;1{ic}|PMOS4f@0||30.5|19|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S19.5
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NOff-Page|conn@3||7.5|8||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)SPMOS4f
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S4-terminal standard threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@6|||0|conn@3|a|5.5|8|pmos4p@0|b|0|8
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f_high;1{ic}
+CPMOS4f_high;1{ic}||artwork|1021415734000|1245267416583|E|ATTR_Delay(D5G1;HNPTX2.5;Y-2;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX2.5;Y1;)S4|ATTR_M1(D5G1;HNOLPX2.5;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2.5;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2.5;Y2;)S19.5|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3.5|0|||RR|
+NPin|pin@9||-3|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-2|1|1|1|Y|
+NPin|pin@12||-2|-1|1|1|Y|
+Nschematic:Bus_Pin|pin@13||0|0.5|-2|-2||
+NPin|pin@15||-0.5|0.25|1|1|YRR|
+NPin|pin@16||-0.5|0.75|1|1|YRR|
+NPin|pin@17||-0.75|0.5|1|1|Y|
+NPin|pin@18||0|0.5||||
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3.5|0|pin@9||-3|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-2|-1|pin@11||-2|1|ART_color()I74
+AThicker|net@8|||FS3150|pin@15||-0.5|0.25|pin@17||-0.75|0.5|ART_color()I74
+AThicker|net@9|||FS450|pin@16||-0.5|0.75|pin@17||-0.75|0.5|ART_color()I74
+AThicker|net@10|||FS0|pin@18||0|0.5|pin@17||-0.75|0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOS4f_high;1{sch}
+CPMOS4f_high;1{sch}||schematic|1021415734000|1245267410230||ATTR_Delay(D5G1;HNPTX-7;Y0.75;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX-7;Y3;)S4|ATTR_M1(D5G1;HNOLPX-7;Y-1;)S1|ATTR_NF(D5G1;HNOLPX-7;Y2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-7;Y4;)S19.5|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SXM$(node_name) $(d) $(g) $(s) $(b) pch_hvt_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f_high;1{ic}|PMOS4f_h@0||30.5|19|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S19.5
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NOff-Page|conn@3||7.5|8||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)SPMOS4f_high
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S4-terminal high threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch_hvt
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@6|||0|conn@3|a|5.5|8|pmos4p@0|b|0|8
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f_io18;1{ic}
+CPMOS4f_io18;1{ic}||artwork|1021415734000|1244051454159|E|ATTR_Delay(D5G1;HNPTX2.5;Y-2;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX2.5;Y1;)S15|ATTR_M1(D5G1;HNOLPX2.5;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2.5;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2.5;Y2;)S32|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3.5|0|||RR|
+NPin|pin@9||-3|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-2|1|1|1|Y|
+NPin|pin@12||-2|-1|1|1|Y|
+Nschematic:Bus_Pin|pin@13||0|0.5|-2|-2||
+NPin|pin@15||-0.5|0.25|1|1|YRR|
+NPin|pin@16||-0.5|0.75|1|1|YRR|
+NPin|pin@17||-0.75|0.5|1|1|Y|
+NPin|pin@18||0|0.5||||
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3.5|0|pin@9||-3|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-2|-1|pin@11||-2|1|ART_color()I74
+AThicker|net@8|||FS3150|pin@15||-0.5|0.25|pin@17||-0.75|0.5|ART_color()I74
+AThicker|net@9|||FS450|pin@16||-0.5|0.75|pin@17||-0.75|0.5|ART_color()I74
+AThicker|net@10|||FS0|pin@18||0|0.5|pin@17||-0.75|0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOS4f_io18;1{sch}
+CPMOS4f_io18;1{sch}||schematic|1021415734000|1245272145423||ATTR_Delay(D5G1;HNPTX-7;Y0.75;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX-7;Y3;)S15|ATTR_M1(D5G1;HNOLPX-7;Y-1;)S1|ATTR_NF(D5G1;HNOLPX-7;Y2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-7;Y4;)S32|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SXM$(node_name) $(d) $(g) $(s) $(b) pch_18_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f_io18;1{ic}|PMOS4f_i@0||32.5|16|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S15|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S32
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NOff-Page|conn@3||7.5|8||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|28.5|||||ART_message(D5G6;)SPMOS4f_io18
+Ngeneric:Invisible-Pin|pin@3||-0.5|23.5|||||ART_message(D5G2;)S4-terminal PMOS device for 1.8V I/O pads
+Ngeneric:Invisible-Pin|pin@4||0|20|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 15 (0.15um)
+Ngeneric:Invisible-Pin|pin@5||0|18|||||ART_message(D5G2;)Sminimum width is 32 (0.32um)
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch_18
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@6|||0|conn@3|a|5.5|8|pmos4p@0|b|0|8
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f_low;1{ic}
+CPMOS4f_low;1{ic}||artwork|1021415734000|1245267557772|E|ATTR_Delay(D5G1;HNPTX2.5;Y-2;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX2.5;Y1;)S4|ATTR_M1(D5G1;HNOLPX2.5;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2.5;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2.5;Y2;)S19.5|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.5|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3|0|||RR|
+NPin|pin@9||-2|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-1|1|1|1|Y|
+NPin|pin@12||-1|-1|1|1|Y|
+Nschematic:Bus_Pin|pin@13||0|0.5|-2|-2||
+NPin|pin@15||-0.5|0.25|1|1|YRR|
+NPin|pin@16||-0.5|0.75|1|1|YRR|
+NPin|pin@17||-0.75|0.5|1|1|Y|
+NPin|pin@18||0|0.5||||
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3|0|pin@9||-2|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-1|-1|pin@11||-1|1|ART_color()I74
+AThicker|net@8|||FS3150|pin@15||-0.5|0.25|pin@17||-0.75|0.5|ART_color()I74
+AThicker|net@9|||FS450|pin@16||-0.5|0.75|pin@17||-0.75|0.5|ART_color()I74
+AThicker|net@10|||FS0|pin@18||0|0.5|pin@17||-0.75|0.5|ART_color()I74
+Eb||D5G1;|pin@13||B
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOS4f_low;1{sch}
+CPMOS4f_low;1{sch}||schematic|1021415734000|1245267548555||ATTR_Delay(D5G1;HNPTX-7;Y0.75;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX-7;Y3;)S4|ATTR_M1(D5G1;HNOLPX-7;Y-1;)S1|ATTR_NF(D5G1;HNOLPX-7;Y2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-7;Y4;)S19.5|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SXM$(node_name) $(d) $(g) $(s) $(b) pch_lvt_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f_low;1{ic}|PMOS4f_l@0||30.5|19|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S19.5
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NOff-Page|conn@3||7.5|8||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)SPMOS4f_low
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S4-terminal low threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch_lvt
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@6|||0|conn@3|a|5.5|8|pmos4p@0|b|0|8
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSf;1{ic}
+CPMOSf;1{ic}||artwork|1021415734000|1241201289354|E|ATTR_Delay(D5G1;HNPTX2.5;Y-2;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX2.5;Y1;)S4|ATTR_M1(D5G1;HNOLPX2.5;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2.5;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2.5;Y2;)S19.5|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3|0|||RR|
+NPin|pin@9||-2.5|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-1.5|1|1|1|Y|
+NPin|pin@12||-1.5|-1|1|1|Y|
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3|0|pin@9||-2.5|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-1.5|-1|pin@11||-1.5|1|ART_color()I74
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSf;1{sch}
+CPMOSf;1{sch}||schematic|1021415734000|1243981039318||ATTR_Delay(D5G1;HNPTX-7;Y0.75;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX-7;Y3;)S4|ATTR_M1(D5G1;HNOLPX-7;Y-1;)S1|ATTR_NF(D5G1;HNOLPX-7;Y2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-7;Y4;)S19.5|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SXM$(node_name) $(d) $(g) $(s) vdd pch_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf;1{ic}|PMOSf@1||30.5|19|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S19.5
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)S[PMOSf]
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S3-terminal standard threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_M(D5G1;NOLX-2.5;Y-4;)S@M1|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch
+NPower|pwr@0||6|8||||
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSf_high;1{ic}
+CPMOSf_high;1{ic}||artwork|1021415734000|1245267359976|E|ATTR_Delay(D5G1;HNPTX2.5;Y-2;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX2.5;Y1;)S4|ATTR_M1(D5G1;HNOLPX2.5;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2.5;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2.5;Y2;)S19.5|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3.5|0|||RR|
+NPin|pin@9||-3|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-2|1|1|1|Y|
+NPin|pin@12||-2|-1|1|1|Y|
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3.5|0|pin@9||-3|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-2|-1|pin@11||-2|1|ART_color()I74
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSf_high;1{sch}
+CPMOSf_high;1{sch}||schematic|1021415734000|1245267318423||ATTR_Delay(D5G1;HNPTX-7;Y0.75;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX-7;Y3;)S4|ATTR_M1(D5G1;HNOLPX-7;Y-1;)S1|ATTR_NF(D5G1;HNOLPX-7;Y2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-7;Y4;)S19.5|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SXM$(node_name) $(d) $(g) $(s) vdd pch_hvt_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_high;1{ic}|PMOSf_hi@0||30.5|19|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S19.5
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)SPMOSf_high
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S3-terminal high threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_M(D5G1;NOLX-2.5;Y-4;)S@M1|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch_hvt
+NPower|pwr@0||6|8||||
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSf_io18;1{ic}
+CPMOSf_io18;1{ic}||artwork|1021415734000|1244051446911|E|ATTR_Delay(D5G1;HNPTX2.5;Y-2;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX2.5;Y1;)S4|ATTR_M1(D5G1;HNOLPX2.5;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2.5;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2.5;Y2;)S32|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3.5|0|||RR|
+NPin|pin@9||-3|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-2|1|1|1|Y|
+NPin|pin@12||-2|-1|1|1|Y|
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3.5|0|pin@9||-3|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-2|-1|pin@11||-2|1|ART_color()I74
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSf_io18;1{sch}
+CPMOSf_io18;1{sch}||schematic|1021415734000|1245272151193||ATTR_Delay(D5G1;HNPTX-7;Y0.75;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX-7;Y3;)S4|ATTR_M1(D5G1;HNOLPX-7;Y-1;)S1|ATTR_NF(D5G1;HNOLPX-7;Y2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-7;Y4;)S32|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) vdd pch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SXM$(node_name) $(d) $(g) $(s) vdd pch_18_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) vdd pch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) vdd pch_18 W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_io18;1{ic}|PMOSf_io@0||34|21|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S32
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|29.5|||||ART_message(D5G6;)SPMOSf_io18
+Ngeneric:Invisible-Pin|pin@3||-0.5|24.5|||||ART_message(D5G2;)S3-terminal PMOS device for 1.8V I/O pads
+Ngeneric:Invisible-Pin|pin@4||0.5|20|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 15 (0.15um)
+Ngeneric:Invisible-Pin|pin@5||-1|18|||||ART_message(D5G2;)Sminimum width is 32 (0.32um)
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_M(D5G1;NOLX-2.5;Y-3;)S@M1|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch_18
+NPower|pwr@0||6|8||||
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSf_low;1{ic}
+CPMOSf_low;1{ic}||artwork|1021415734000|1245267503892|E|ATTR_Delay(D5G1;HNPTX2.5;Y-2;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX2.5;Y1;)S4|ATTR_M1(D5G1;HNOLPX2.5;Y-1;)S1|ATTR_NF(D5G1;HNOLPX2.5;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX2.5;Y2;)S19.5|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.5|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3|0|||RR|
+NPin|pin@9||-2|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-1|1|1|1|Y|
+NPin|pin@12||-1|-1|1|1|Y|
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3|0|pin@9||-2|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-1|-1|pin@11||-1|1|ART_color()I74
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSf_low;1{sch}
+CPMOSf_low;1{sch}||schematic|1021415734000|1245267494503||ATTR_Delay(D5G1;HNPTX-7;Y0.75;)S10|ATTR_L(D5FLeave alone;G1;HNOLPX-7;Y3;)S4|ATTR_M1(D5G1;HNOLPX-7;Y-1;)S1|ATTR_NF(D5G1;HNOLPX-7;Y2;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-7;Y4;)S19.5|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SXM$(node_name) $(d) $(g) $(s) vdd pch_lvt_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_low;1{ic}|PMOSf_lo@0||30.5|19|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S4|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S19.5
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)SPMOSf_low
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S3-terminal low threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_M(D5G1;NOLX-2.5;Y-4;)S@M1|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch_lvt
+NPower|pwr@0||6|8||||
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PNP2;1{ic}
+CPNP2;1{ic}||artwork|1247267653522|1247268063932|E
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Nschematic:Bus_Pin|pin@0||-2|0||||
+Nschematic:Bus_Pin|pin@2||2|-4||||
+Nschematic:Bus_Pin|pin@4||2|4||||
+NPin|pin@6||0|2|1|1||
+NPin|pin@7||0|-2|1|1||
+NPin|pin@8||0|0|1|1||
+NPin|pin@9||-2|0|1|1||
+NPin|pin@10||0|-1|1|1||
+NPin|pin@11||2|-2.5|1|1||
+NPin|pin@12||2|-2.5|1|1||
+NPin|pin@13||2|-4|1|1||
+NPin|pin@14||0|1|1|1|Y|
+NPin|pin@15||2|2.5|1|1|Y|
+NPin|pin@16||2|4|1|1||
+NPin|pin@17||2|2.5|1|1||
+NPin|pin@18||0|1|1|1|Y|
+NPin|pin@19||0.5|1|1|1|Y|
+NPin|pin@20||0|1|1|1|Y|
+NPin|pin@21||0.2|1.45|1|1|Y|
+Ngeneric:Invisible-Pin|pin@22||2.5|0|||||ART_message(D5G1.5;)SPNP2
+AThicker|net@3|||FS900|pin@6||0|2|pin@7||0|-2|ART_color()I-3407871
+AThicker|net@4|||FS0|pin@8||0|0|pin@9||-2|0|ART_color()I-3407871
+AThicker|net@5|||FS1431|pin@10||0|-1|pin@11||2|-2.5|ART_color()I-3407871
+AThicker|net@6|||FS900|pin@12||2|-2.5|pin@13||2|-4|ART_color()I-3407871
+AThicker|net@7|||FS2169|pin@14||0|1|pin@15||2|2.5|ART_color()I-3407871
+AThicker|net@8|||FS900|pin@16||2|4|pin@17||2|2.5|ART_color()I-3407871
+AThicker|net@9|||FS1800|pin@18||0|1|pin@19||0.5|1|ART_color()I-3407871
+AThicker|net@10|||FS2460|pin@20||0|1|pin@21||0.2|1.45|ART_color()I-3407871
+Ebase||D5G2;|pin@0||I
+Ecollector||D5G2;|pin@2||B
+Eemitter||D5G2;|pin@4||B
+X
+
+# Cell PNP2;1{sch}
+CPNP2;1{sch}||schematic|1247267536794|1247268071289||ATTR_NCC(D5G1;NTX-28;Y-10.5;)SblackBox electric does not understand bipolar transistors|ATTR_SPICE_template(D5G1;NTX-28;Y-12.5;)SQ$(node_name) $(collector) $(base) $(emitter) pnp2 area=4p|ATTR_SPICE_template_calibre(D5G1;NTX-28;Y-14.5;)SQ$(node_name) $(collector) $(base) $(emitter) pnp2
+IPNP2;1{ic}|PNP2@0||-3|15|||D5G4;
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-26|15|||RRR|
+NOff-Page|conn@1||-26|-3|||R|
+NOff-Page|conn@2||-35|6||||
+Ngeneric:Invisible-Pin|pin@0||-26.5|29|||||ART_message(D5G5;)SPNP2
+Ngeneric:Invisible-Pin|pin@1||-26|23|||||ART_message(D5G2;)Spnp bipolar transistor with 2x2 emitter
+NTransistor|pnp@0||-28|6|||YR|4|ATTR_area(D5G1;Y-2.5;)S4e-12
+Awire|net@0|||1800|conn@2|y|-33|6|pnp@0|g|-29|6
+Awire|net@1|||2700|conn@1|y|-26|-1|pnp@0|d|-26|4
+Awire|net@2|||900|conn@0|y|-26|13|pnp@0|s|-26|8
+Ebase||D5G2;|conn@2|a|I
+Ecollector||D5G2;|conn@1|a|B
+Eemitter||D5G2;|conn@0|a|B
+X
+
+# Cell PNP5;1{ic}
+CPNP5;1{ic}||artwork|1247267653522|1247268045385|E
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Nschematic:Bus_Pin|pin@0||-2|0||||
+Nschematic:Bus_Pin|pin@2||2|-4||||
+Nschematic:Bus_Pin|pin@4||2|4||||
+NPin|pin@6||0|2|1|1||
+NPin|pin@7||0|-2|1|1||
+NPin|pin@8||0|0|1|1||
+NPin|pin@9||-2|0|1|1||
+NPin|pin@10||0|-1|1|1||
+NPin|pin@11||2|-2.5|1|1||
+NPin|pin@12||2|-2.5|1|1||
+NPin|pin@13||2|-4|1|1||
+NPin|pin@14||0|1|1|1|Y|
+NPin|pin@15||2|2.5|1|1|Y|
+NPin|pin@16||2|4|1|1||
+NPin|pin@17||2|2.5|1|1||
+NPin|pin@18||0|1|1|1|Y|
+NPin|pin@19||0.5|1|1|1|Y|
+NPin|pin@20||0|1|1|1|Y|
+NPin|pin@21||0.2|1.45|1|1|Y|
+Ngeneric:Invisible-Pin|pin@22||2.5|0|||||ART_message(D5G1.5;)SPNP5
+AThicker|net@3|||FS900|pin@6||0|2|pin@7||0|-2|ART_color()I-3407871
+AThicker|net@4|||FS0|pin@8||0|0|pin@9||-2|0|ART_color()I-3407871
+AThicker|net@5|||FS1431|pin@10||0|-1|pin@11||2|-2.5|ART_color()I-3407871
+AThicker|net@6|||FS900|pin@12||2|-2.5|pin@13||2|-4|ART_color()I-3407871
+AThicker|net@7|||FS2169|pin@14||0|1|pin@15||2|2.5|ART_color()I-3407871
+AThicker|net@8|||FS900|pin@16||2|4|pin@17||2|2.5|ART_color()I-3407871
+AThicker|net@9|||FS1800|pin@18||0|1|pin@19||0.5|1|ART_color()I-3407871
+AThicker|net@10|||FS2460|pin@20||0|1|pin@21||0.2|1.45|ART_color()I-3407871
+Ebase||D5G2;|pin@0||I
+Ecollector||D5G2;|pin@2||B
+Eemitter||D5G2;|pin@4||B
+X
+
+# Cell PNP5;1{sch}
+CPNP5;1{sch}||schematic|1247267536794|1247267955820||ATTR_NCC(D5G1;NTX-28;Y-10.5;)SblackBox electric does not understand bipolar transistors|ATTR_SPICE_template(D5G1;NTX-28;Y-12.5;)SQ$(node_name) $(collector) $(base) $(emitter) pnp5 area=25p|ATTR_SPICE_template_calibre(D5G1;NTX-28;Y-14.5;)SQ$(node_name) $(collector) $(base) $(emitter) pnp5
+IPNP5;1{ic}|PNP5@0||-3|15|||D5G4;
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-26|15|||RRR|
+NOff-Page|conn@1||-26|-3|||R|
+NOff-Page|conn@2||-35|6||||
+Ngeneric:Invisible-Pin|pin@0||-26.5|29|||||ART_message(D5G5;)SPNP5
+Ngeneric:Invisible-Pin|pin@1||-26|23|||||ART_message(D5G2;)Spnp bipolar transistor with 5x5 emitter
+NTransistor|pnp@0||-28|6|||YR|4|ATTR_area(D5G1;Y-2.5;)S25e-12
+Awire|net@0|||1800|conn@2|y|-33|6|pnp@0|g|-29|6
+Awire|net@1|||2700|conn@1|y|-26|-1|pnp@0|d|-26|4
+Awire|net@2|||900|conn@0|y|-26|13|pnp@0|s|-26|8
+Eemitter_1@803456730|base|D5G2;|conn@2|a|I
+Eemitter_1|collector|D5G2;|conn@1|a|B
+Eemitter||D5G2;|conn@0|a|B
+X
+
+# Cell PNP10;1{ic}
+CPNP10;1{ic}||artwork|1247267653522|1247268123489|E
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Nschematic:Bus_Pin|pin@0||-2|0||||
+Nschematic:Bus_Pin|pin@2||2|-4||||
+Nschematic:Bus_Pin|pin@4||2|4||||
+NPin|pin@6||0|2|1|1||
+NPin|pin@7||0|-2|1|1||
+NPin|pin@8||0|0|1|1||
+NPin|pin@9||-2|0|1|1||
+NPin|pin@10||0|-1|1|1||
+NPin|pin@11||2|-2.5|1|1||
+NPin|pin@12||2|-2.5|1|1||
+NPin|pin@13||2|-4|1|1||
+NPin|pin@14||0|1|1|1|Y|
+NPin|pin@15||2|2.5|1|1|Y|
+NPin|pin@16||2|4|1|1||
+NPin|pin@17||2|2.5|1|1||
+NPin|pin@18||0|1|1|1|Y|
+NPin|pin@19||0.5|1|1|1|Y|
+NPin|pin@20||0|1|1|1|Y|
+NPin|pin@21||0.2|1.45|1|1|Y|
+Ngeneric:Invisible-Pin|pin@22||2.5|0|||||ART_message(D5G1.5;)SPNP10
+AThicker|net@3|||FS900|pin@6||0|2|pin@7||0|-2|ART_color()I-3407871
+AThicker|net@4|||FS0|pin@8||0|0|pin@9||-2|0|ART_color()I-3407871
+AThicker|net@5|||FS1431|pin@10||0|-1|pin@11||2|-2.5|ART_color()I-3407871
+AThicker|net@6|||FS900|pin@12||2|-2.5|pin@13||2|-4|ART_color()I-3407871
+AThicker|net@7|||FS2169|pin@14||0|1|pin@15||2|2.5|ART_color()I-3407871
+AThicker|net@8|||FS900|pin@16||2|4|pin@17||2|2.5|ART_color()I-3407871
+AThicker|net@9|||FS1800|pin@18||0|1|pin@19||0.5|1|ART_color()I-3407871
+AThicker|net@10|||FS2460|pin@20||0|1|pin@21||0.2|1.45|ART_color()I-3407871
+Ebase||D5G2;|pin@0||I
+Ecollector||D5G2;|pin@2||B
+Eemitter||D5G2;|pin@4||B
+X
+
+# Cell PNP10;1{sch}
+CPNP10;1{sch}||schematic|1247267536794|1247268137920||ATTR_NCC(D5G1;NTX-28;Y-10.5;)SblackBox electric does not understand bipolar transistors|ATTR_SPICE_template(D5G1;NTX-28;Y-12.5;)SQ$(node_name) $(collector) $(base) $(emitter) pnp10 area=100p|ATTR_SPICE_template_calibre(D5G1;NTX-28;Y-14.5;)SQ$(node_name) $(collector) $(base) $(emitter) pnp10
+IPNP10;1{ic}|PNP10@0||-3|15|||D5G4;
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-26|15|||RRR|
+NOff-Page|conn@1||-26|-3|||R|
+NOff-Page|conn@2||-35|6||||
+Ngeneric:Invisible-Pin|pin@0||-26.5|29|||||ART_message(D5G5;)SPNP10
+Ngeneric:Invisible-Pin|pin@1||-26|23|||||ART_message(D5G2;)Spnp bipolar transistor with 10x10 emitter
+NTransistor|pnp@0||-28|6|||YR|4|ATTR_area(D5G1;Y-2.5;)S100e-12
+Awire|net@0|||1800|conn@2|y|-33|6|pnp@0|g|-29|6
+Awire|net@1|||2700|conn@1|y|-26|-1|pnp@0|d|-26|4
+Awire|net@2|||900|conn@0|y|-26|13|pnp@0|s|-26|8
+Ebase||D5G2;|conn@2|a|I
+Ecollector||D5G2;|conn@1|a|B
+Eemitter||D5G2;|conn@0|a|B
+X
+
+# Cell R128;1{ic}
+CR128;1{ic}||artwork|1047945855000|1245913852790|E|ATTR_L(D5FLeave alone;G1;HNOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX2.25;Y-2.25;)S40|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||3|0|1|1|Y|
+NPin|pin@1||2|0|1|1|Y|
+NPin|pin@2||1.5|-1|1|1|Y|
+NPin|pin@3||1|1|1|1|Y|
+NPin|pin@4||0.5|-1|1|1|Y|
+NPin|pin@5||0|1|1|1|Y|
+NPin|pin@6||-0.5|-1|1|1|Y|
+NPin|pin@7||-1|1|1|1|Y|
+NPin|pin@8||-1.5|-1|1|1|Y|
+NPin|pin@9||-2|0|1|1|Y|
+NPin|pin@10||-3|0|1|1|Y|
+Nschematic:Bus_Pin|pin@11||3|0||||
+Nschematic:Bus_Pin|pin@12||-3|0||||
+NPin|pin@13||-2.5|-0.75|1|1||
+NPin|pin@14||2.5|-0.75|1|1||
+NPin|pin@15||0|-1.5|1|1|YRRR|
+NPin|pin@16||0|-0.75|1|1|YRRR|
+NPin|pin@18||1|-1.5|1|1|YRR|
+NPin|pin@19||-1|-1.5|1|1|YRR|
+NPin|pin@20||0.5|-2|1|1|YRR|
+NPin|pin@21||-0.5|-2|1|1|YRR|
+Ngeneric:Invisible-Pin|pin@22||0.5|1|||||ART_message(D5G1;)S128
+AThicker|net@0|||FS1800|pin@1||2|0|pin@0||3|0|ART_color()I74
+AThicker|net@1|||FS2434|pin@2||1.5|-1|pin@1||2|0|ART_color()I74
+AThicker|net@2|||FS1040|pin@3||1|1|pin@2||1.5|-1|ART_color()I74
+AThicker|net@3|||FS2560|pin@4||0.5|-1|pin@3||1|1|ART_color()I74
+AThicker|net@4|||FS1040|pin@5||0|1|pin@4||0.5|-1|ART_color()I74
+AThicker|net@5|||FS2560|pin@6||-0.5|-1|pin@5||0|1|ART_color()I74
+AThicker|net@6|||FS1040|pin@7||-1|1|pin@6||-0.5|-1|ART_color()I74
+AThicker|net@7|||FS2560|pin@8||-1.5|-1|pin@7||-1|1|ART_color()I74
+AThicker|net@8|||FS1166|pin@9||-2|0|pin@8||-1.5|-1|ART_color()I74
+AThicker|net@9|||FS1800|pin@10||-3|0|pin@9||-2|0|ART_color()I74
+AThicker|net@10|||FS1800|pin@13||-2.5|-0.75|pin@14||2.5|-0.75|ART_color()I74
+AThicker|net@11|||FS2700|pin@15||0|-1.5|pin@16||0|-0.75|ART_color()I74
+AThicker|net@12|||FS0|pin@18||1|-1.5|pin@19||-1|-1.5|ART_color()I74
+AThicker|net@13|||FS0|pin@20||0.5|-2|pin@21||-0.5|-2|ART_color()I74
+Ein||D5G2;|pin@12||I
+Eout||D5G2;|pin@11||O
+X
+
+# Cell R128;1{sch}
+CR128;1{sch}||schematic|1047945706000|1245967487005||ATTR_L(D5FLeave alone;G1;HNOLPX-22.5;Y-0.75;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX-22.25;Y-1.75;)S40|ATTR_CDL_template(D5G1;NTX-2.5;Y-14;)SXR$(node_name) $(in) $(out) /rnpolywo l='$(L)*10n' w='$(W)*10n'|ATTR_NCC(D5G1;NTX-1.5;Y-18.5;)SresistorType  N-Poly-RPO-Resistor|ATTR_SPICE_template_assura(D5G1;NTX0.5;Y-23;)SXR$(node_name) $(in) $(out) rnpolywo l='$(L)*10n' w='$(W)*10n'|ATTR_SPICE_template_calibre(D5G1;NTX0.5;Y-21;)SXR$(node_name) $(in) $(out) rnpolywo l='$(L)*10n' w='$(W)*10n'|ATTR_SPICE_template_hspice(D5G1;NTX-1.5;Y-16.25;)SXR$(node_name) $(in) $(out) rnpolywo l='$(L)*10n' w='$(W)*10n'|ATTR_SPICE_template_smartspice(D5G1;NTY-12;)SXR$(node_name) $(in) $(out) rnpolywo l='$(L)*10n' w='$(W)*10n'|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||-5.5|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NCapacitor|cap@1||4.75|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NOff-Page|conn@0||10|5||||
+NOff-Page|conn@1||-11.5|5||||
+IR128;1{ic}|gateResi@0||25.5|7.5|||D0G4;|ATTR_L(D5FLeave alone;G1;NOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;NOLPX2.25;Y-2.25;)S40
+NGround|gnd@0||0|-8.5||||
+Ngeneric:Invisible-Pin|pin@0||1|20.5|||||ART_message(D5G2;)Sn-type unsilicided polysilicon resistor for TSMC90nm process
+Ngeneric:Invisible-Pin|pin@1||2.5|26.5|||||ART_message(D5G5;)SR128 (rnpolywo)
+NWire_Pin|pin@2||-5.5|5||||
+NWire_Pin|pin@3||-5.5|-4.5||||
+NWire_Pin|pin@4||4.75|5||||
+NWire_Pin|pin@5||4.75|-4.5||||
+Ngeneric:Invisible-Pin|pin@6||1.5|15|||||ART_message(D5G2;)S["minumum recommended dimensions are l=0.4um, w=0.4um",target resistance is approx 128 ohm/sq]
+NWire_Pin|pin@7||0|-4.5||||
+NResistor|res@0||-0.5|5||||1|ATTR_length(D5FLeave alone;G1;NOLY-1;)S@L|ATTR_width(D5FLeave alone;G1;NOLY-2;)S@W|SCHEM_resistance(D5FLeave alone;G2;OLY1.5;)S(@L*128/@W)
+Awire|net@0|||0|pin@2||-5.5|5|conn@1|y|-9.5|5
+Awire|net@1|||1800|pin@4||4.75|5|conn@0|a|8|5
+Awire|net@2|||0|res@0|a|-2.5|5|pin@2||-5.5|5
+Awire|net@3|||2700|cap@0|a|-5.5|2|pin@2||-5.5|5
+Awire|net@4|||900|cap@0|b|-5.5|-2|pin@3||-5.5|-4.5
+Awire|net@6|||1800|res@0|b|1.5|5|pin@4||4.75|5
+Awire|net@7|||2700|cap@1|a|4.75|2|pin@4||4.75|5
+Awire|net@8|||900|cap@1|b|4.75|-2|pin@5||4.75|-4.5
+Awire|net@9|||0|pin@7||0|-4.5|pin@3||-5.5|-4.5
+Awire|net@10|||0|pin@5||4.75|-4.5|pin@7||0|-4.5
+Awire|net@11|||2700|gnd@0||0|-6.5|pin@7||0|-4.5
+Ein||D5G2;|conn@1|y|I
+Eout||D5G2;|conn@0|y|O
+X
+
+# Cell R810;1{ic}
+CR810;1{ic}||artwork|1047945855000|1245913994391|E|ATTR_L(D5FLeave alone;G1;HNOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX2.25;Y-2.25;)S40|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||3|0|1|1|Y|
+NPin|pin@1||2|0|1|1|Y|
+NPin|pin@2||1.5|-1|1|1|Y|
+NPin|pin@3||1|1|1|1|Y|
+NPin|pin@4||0.5|-1|1|1|Y|
+NPin|pin@5||0|1|1|1|Y|
+NPin|pin@6||-0.5|-1|1|1|Y|
+NPin|pin@7||-1|1|1|1|Y|
+NPin|pin@8||-1.5|-1|1|1|Y|
+NPin|pin@9||-2|0|1|1|Y|
+NPin|pin@10||-3|0|1|1|Y|
+Nschematic:Bus_Pin|pin@11||3|0||||
+Nschematic:Bus_Pin|pin@12||-3|0||||
+NPin|pin@13||-2.5|-0.75|1|1||
+NPin|pin@14||2.5|-0.75|1|1||
+NPin|pin@15||0|-1.5|1|1|YRRR|
+NPin|pin@16||0|-0.75|1|1|YRRR|
+NPin|pin@18||1|-1.5|1|1|YRR|
+NPin|pin@19||-1|-1.5|1|1|YRR|
+NPin|pin@20||0.5|-2|1|1|YRR|
+NPin|pin@21||-0.5|-2|1|1|YRR|
+Ngeneric:Invisible-Pin|pin@22||0.5|1|||||ART_message(D5G1;)S810
+AThicker|net@0|||FS1800|pin@1||2|0|pin@0||3|0|ART_color()I74
+AThicker|net@1|||FS2434|pin@2||1.5|-1|pin@1||2|0|ART_color()I74
+AThicker|net@2|||FS1040|pin@3||1|1|pin@2||1.5|-1|ART_color()I74
+AThicker|net@3|||FS2560|pin@4||0.5|-1|pin@3||1|1|ART_color()I74
+AThicker|net@4|||FS1040|pin@5||0|1|pin@4||0.5|-1|ART_color()I74
+AThicker|net@5|||FS2560|pin@6||-0.5|-1|pin@5||0|1|ART_color()I74
+AThicker|net@6|||FS1040|pin@7||-1|1|pin@6||-0.5|-1|ART_color()I74
+AThicker|net@7|||FS2560|pin@8||-1.5|-1|pin@7||-1|1|ART_color()I74
+AThicker|net@8|||FS1166|pin@9||-2|0|pin@8||-1.5|-1|ART_color()I74
+AThicker|net@9|||FS1800|pin@10||-3|0|pin@9||-2|0|ART_color()I74
+AThicker|net@10|||FS1800|pin@13||-2.5|-0.75|pin@14||2.5|-0.75|ART_color()I74
+AThicker|net@11|||FS2700|pin@15||0|-1.5|pin@16||0|-0.75|ART_color()I74
+AThicker|net@12|||FS0|pin@18||1|-1.5|pin@19||-1|-1.5|ART_color()I74
+AThicker|net@13|||FS0|pin@20||0.5|-2|pin@21||-0.5|-2|ART_color()I74
+Ein||D5G2;|pin@12||I
+Eout||D5G2;|pin@11||O
+X
+
+# Cell R810;1{sch}
+CR810;1{sch}||schematic|1047945706000|1245967559591||ATTR_L(D5FLeave alone;G1;HNOLPX-22.5;Y-0.75;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX-22.25;Y-1.75;)S40|ATTR_CDL_template(D5G1;NTX-2.5;Y-16.5;)SXR$(node_name) $(in) $(out) /rppolywo l='$(L)*10n' w='$(W)*10n'|ATTR_NCC(D5G1;NTX-1.5;Y-21;)SresistorType  P-Poly-RPO-Resistor|ATTR_SPICE_template_assura(D5G1;NTX-1.5;Y-25;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)*10n' w='$(W)*10n'|ATTR_SPICE_template_calibre(D5G1;NTX-1.5;Y-23;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)*10n' w='$(W)*10n'|ATTR_SPICE_template_hspice(D5G1;NTX-1.5;Y-18.75;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)*10n' w='$(W)*10n'|ATTR_SPICE_template_smartspice(D5G1;NTX-1;Y-14;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)*10n' w='$(W)*10n'|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||-5.5|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NCapacitor|cap@1||4.75|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NOff-Page|conn@0||10|5||||
+NOff-Page|conn@1||-11.5|5||||
+IR810;1{ic}|gateResi@0||25.5|7.5|||D0G4;|ATTR_L(D5FLeave alone;G1;NOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;NOLPX2.25;Y-2.25;)S40
+NGround|gnd@0||0|-9||||
+Ngeneric:Invisible-Pin|pin@0||1|20.5|||||ART_message(D5G2;)Sp-type unsilicided polysilicon resistor for TSMC90nm process
+Ngeneric:Invisible-Pin|pin@1||2.5|26.5|||||ART_message(D5G5;)SR810 (rppolywo)
+NWire_Pin|pin@2||-5.5|5||||
+NWire_Pin|pin@3||-5.5|-4.5||||
+NWire_Pin|pin@4||4.75|5||||
+NWire_Pin|pin@5||4.75|-4.5||||
+Ngeneric:Invisible-Pin|pin@6||1.5|15|||||ART_message(D5G2;)S["minumum recommended dimensions are l=0.4um, w=0.4um",target resistance is approx 810 ohm/sq]
+NWire_Pin|pin@7||0|-4.5||||
+NResistor|pres@0||0|5||||1|ATTR_length(D5FLeave alone;G1;NOLY-1;)S@L|ATTR_width(D5FLeave alone;G1;NOLY-2;)S@W|SCHEM_resistance(D5FLeave alone;G2;OLY1.5;)S(@L*810/@W)
+Awire|net@0|||0|pin@2||-5.5|5|conn@1|y|-9.5|5
+Awire|net@1|||1800|pin@4||4.75|5|conn@0|a|8|5
+Awire|net@3|||2700|cap@0|a|-5.5|2|pin@2||-5.5|5
+Awire|net@4|||900|cap@0|b|-5.5|-2|pin@3||-5.5|-4.5
+Awire|net@7|||2700|cap@1|a|4.75|2|pin@4||4.75|5
+Awire|net@8|||900|cap@1|b|4.75|-2|pin@5||4.75|-4.5
+Awire|net@9|||0|pin@7||0|-4.5|pin@3||-5.5|-4.5
+Awire|net@10|||0|pin@5||4.75|-4.5|pin@7||0|-4.5
+Awire|net@11|||2700|gnd@0||0|-7|pin@7||0|-4.5
+Awire|net@12|||1800|pres@0|b|2|5|pin@4||4.75|5
+Awire|net@13|||0|pres@0|a|-2|5|pin@2||-5.5|5
+Ein||D5G2;|conn@1|y|I
+Eout||D5G2;|conn@0|y|O
+X
+
+# Cell aGallery;1{sch}
+CaGallery;1{sch}||schematic|1241110136477|1247268145887|
+INMOS4f;1{ic}|NMOS4f@0||-23.5|-3.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S4|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S15
+INMOS4f_dnw;1{ic}|NMOS4f_d@0||-23.5|-11.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S4|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S15
+INMOS4f_io18;1{ic}|NMOS4f_i@0||-34|-3.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S15|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S15
+INMOS4f_native;1{ic}|NMOS4f_n@0||-12|-3.5|||D5G4;|ATTR_Delay(P)I15|ATTR_L(D5FLeave alone;G1;NOLPX3.5;Y1;)S30|ATTR_M1(D5G1;NOLPX3.5;Y-1;)S1|ATTR_NF(D5G1;NOLPX3.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX3.5;Y2;)S15
+INMOSf;1{ic}|NMOSf@1||-23.5|3.5|||D5G4;|ATTR_Delay(P)I15|ATTR_L(D5FLeave alone;G1;NOLPX3.5;Y1;)S4|ATTR_M1(D5G1;NOLPX3.5;Y-1;)S1|ATTR_NF(D5G1;NOLPX3.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX3.5;Y2;)S15
+INMOSf_io18;1{ic}|NMOSf_io@0||-34|3.5|||D5G4;|ATTR_Delay(P)I15|ATTR_L(D5FLeave alone;G1;NOLPX3.5;Y1;)S15|ATTR_M1(D5G1;NOLPX3.5;Y-1;)S1|ATTR_NF(D5G1;NOLPX3.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX3.5;Y2;)S15
+INMOSf_native;1{ic}|NMOSf_na@0||-12|3.5|||D5G4;|ATTR_Delay(P)I15|ATTR_L(D5FLeave alone;G1;NOLPX3.5;Y1;)S30|ATTR_M1(D5G1;NOLPX3.5;Y-1;)S1|ATTR_NF(D5G1;NOLPX3.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX3.5;Y2;)S15
+IPMOS4f;1{ic}|PMOS4f@0||19.5|-3.5|||D5G4;|ATTR_Delay(P)S10|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S4|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S19.5
+IPMOS4f_io18;1{ic}|PMOS4f_i@0||9.5|-3.5|||D5G4;|ATTR_Delay(P)S10|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S15|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S19.5
+IPMOSf;1{ic}|PMOSf@1||19.5|3.5|||D5G4;|ATTR_Delay(P)S10|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S4|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S19.5
+IPMOSf_io18;1{ic}|PMOSf_io@0||9.5|3.5|||D5G4;|ATTR_Delay(P)S10|ATTR_L(D5FLeave alone;G1;NOLPX4;Y1;)S15|ATTR_M1(D5G1;NOLPX4;Y-1;)S1|ATTR_NF(D5G1;NOLPX4;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y2;)S19.5
+IPNP2;1{ic}|PNP2@0||55.5|1|||D5G4;
+IPNP5;1{ic}|PNP5@0||70|1|||D5G4;
+IPNP10;1{ic}|PNP10@0||83.5|1|||D5G4;
+IR128;1{ic}|R110@0||-29|-29|||D5G4;|ATTR_L(D5FLeave alone;G1;NOLPX-2;Y-1.75;)S40|ATTR_W(D5FLeave alone;G1;NOLPX2.25;Y-1.75;)S"40\\"
+IR810;1{ic}|R440@0||-12|-29|||D5G4;|ATTR_L(D5FLeave alone;G1;NOLPX-2;Y-1.75;)S40|ATTR_W(D5FLeave alone;G1;NOLPX2.25;Y-1.75;)S40
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Iwire40;1{ic}|wire40@0||26|-29|||D5G4;|ATTR_L(D5FLeave alone;G1;OLPUD)S100|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NOLPY-1;)S2|ATTR_width(D5FLeave alone;G1;NOLPY-2;)S7
+Iwire;1{ic}|wire@0||11|-29|||D5G4;|ATTR_C(D5G1;NOLPUCY-2.5;)S0.0000223p|ATTR_L(D5G1;OLPUD)S100|ATTR_R(D5G1;NOLPURY-1.5;)S0.024
+X
+
+# Cell wire;1{ic}
+Cwire;1{ic}||artwork|1083964052000|1204183998562|E|ATTR_C(D5G1;HNOLPUCY-2.5;)S0.0000223p|ATTR_L(D5G1;HOLPUD)S100|ATTR_R(D5G1;HNOLPURY-1.5;)S0.024|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@2||2|0|1.5|1.5|||ART_color()I74
+NPin|pin@0||-2.75|0|1|1||
+NPin|pin@1||-4|0||||
+NPin|pin@2||2|0|1|1||
+NPin|pin@3||4|0||||
+NPin|pin@4||-2|0.75|1|1||
+NPin|pin@5||2|0.75|1|1||
+NPin|pin@6||2|-0.75|1|1||
+NPin|pin@7||-2|-0.75|1|1||
+Nschematic:Bus_Pin|pin@8||4|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||-4|0|-2|-2||
+AThicker|net@0|||IJS0|pin@0||-2.75|0|pin@1||-4|0|ART_color()I74
+AThicker|net@1|||IJS1800|pin@2||2|0|pin@3||4|0|ART_color()I74
+AThicker|net@2|||IJS0|pin@5||2|0.75|pin@4||-2|0.75|ART_color()I74
+AThicker|net@3|||IJS0|pin@6||2|-0.75|pin@7||-2|-0.75|ART_color()I74
+Ea||D5G2;|pin@9||U
+Eb||D5G2;|pin@8||U
+X
+
+# Cell wire;1{sch}
+Cwire;1{sch}||schematic|1083961993000|1173982560561||ATTR_C(D5G1;HNOLPUCX-19;Y-9;)S0.0000223p|ATTR_L(D5G1;HNOLPUDX-19;Y-7;)S100|ATTR_R(D5G1;HNOLPURX-19;Y-8;)S0.024|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||-10|0|||||SCHEM_capacitance(D5G1;OLUC)S@C*@L/3
+NCapacitor|cap@1||10|0|||||SCHEM_capacitance(D5G1;OLUC)S@C*@L/3
+NCapacitor|cap@2||0|0|||||SCHEM_capacitance(D5G1;OLUC)S@C*@L/3
+NOff-Page|conn@0||21|4|||RR|
+NOff-Page|conn@1||-21|4||||
+NGround|gnd@0||0|-8||||
+Ngeneric:Invisible-Pin|pin@0||15|7|||||ART_message(D5G1;)S[R2 ]
+Ngeneric:Invisible-Pin|pin@1||-15|7|||||ART_message(D5G1;)S[R1 = @R*@L/6]
+Ngeneric:Invisible-Pin|pin@2||0|7|||||ART_message(D5G1;)S[R12= @R*@L/3]
+Ngeneric:Invisible-Pin|pin@3||16.5|-2|||||ART_message(D5G1;)S[C = @C*@L/3]
+Ngeneric:Invisible-Pin|pin@4||0|14|||||ART_message(D5G2;)S[this is a wire 'L' lambda long,with resistance 'R' ohms/lambda,and capacitance 'C' F/lambda]
+Ngeneric:Invisible-Pin|pin@5||-1|22|||||ART_message(D5G6;)S[wire]
+NWire_Pin|pin@6||0|-4||||
+NWire_Pin|pin@7||10|-4||||
+NWire_Pin|pin@8||-10|-4||||
+NWire_Pin|pin@9||10|4||||
+NWire_Pin|pin@10||0|4||||
+NWire_Pin|pin@11||-10|4||||
+NResistor|res@0||-15|4|||||SCHEM_resistance(D5G1;OLURY1.5;)S@R*@L/6
+NResistor|res@1||-5|4|||||SCHEM_resistance(D5G1;OLURY1.5;)S@R*@L/3
+NResistor|res@2||15|4|||||SCHEM_resistance(D5G1;OLURY1.5;)S@R*@L/6
+NResistor|res@3||5|4|||||SCHEM_resistance(D5G1;OLURY1.5;)S@R*@L/3
+Iwire;1{ic}|wire@0||15|24|||D0G4;|ATTR_C(D5G1;NOLPUCY-2.5;)S2.23E-16|ATTR_L(D5G1;OLPUD)S100|ATTR_R(D5G1;NOLPURY-1.5;)S0.24
+Awire|net@0|||IJS1800|res@2|b|17|4|conn@0|y|19|4
+Awire|net@1|||IJS0|res@0|a|-17|4|conn@1|y|-19|4
+Awire|net@2|||IJS900|pin@6||0|-4|gnd@0||0|-6
+Awire|net@3|||IJS2700|pin@6||0|-4|cap@2|b|0|-2
+Awire|net@4|||IJS0|pin@7||10|-4|pin@6||0|-4
+Awire|net@5|||IJS0|pin@6||0|-4|pin@8||-10|-4
+Awire|net@6|||IJS900|cap@1|b|10|-2|pin@7||10|-4
+Awire|net@7|||IJS2700|pin@8||-10|-4|cap@0|b|-10|-2
+Awire|net@8|||IJS900|pin@9||10|4|cap@1|a|10|2
+Awire|net@9|||IJS0|res@2|a|13|4|pin@9||10|4
+Awire|net@10|||IJS0|pin@9||10|4|res@3|b|7|4
+Awire|net@11|||IJS900|pin@10||0|4|cap@2|a|0|2
+Awire|net@12|||IJS0|res@3|a|3|4|pin@10||0|4
+Awire|net@13|||IJS0|pin@10||0|4|res@1|b|-3|4
+Awire|net@14|||IJS900|pin@11||-10|4|cap@0|a|-10|2
+Awire|net@15|||IJS0|res@1|a|-7|4|pin@11||-10|4
+Awire|net@16|||IJS0|pin@11||-10|4|res@0|b|-13|4
+Ea||D4G2;|conn@1|a|U
+Eb||D6G2;X-5;|conn@0|y|U
+X
+
+# Cell wire40;1{ic}
+Cwire40;1{ic}||artwork|1083966364000|1244504921853|E|ATTR_L(D5FLeave alone;G1;HOLPUD)S100|ATTR_LEWIRE(D5G1;HPTY-3;)I1|ATTR_layer(D5FLeave alone;G1;HNOLPY-1;)S2|ATTR_width(D5FLeave alone;G1;HNOLPY-2;)S7|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.75|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@2||1.75|0|1.5|1.5|RRR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NPin|pin@0||-1.75|0.75|1|1||
+NPin|pin@1||1.75|0.75|1|1||
+NPin|pin@2||1.75|-0.75|1|1||
+NPin|pin@3||-1.75|-0.75|1|1||
+Nschematic:Bus_Pin|pin@4||2.5|0|-1|-1||
+Nschematic:Bus_Pin|pin@5||-2.5|0|-1|-1||
+AThicker|net@0|||FS0|pin@1||1.75|0.75|pin@0||-1.75|0.75|ART_color()I74
+AThicker|net@1|||FS0|pin@2||1.75|-0.75|pin@3||-1.75|-0.75|ART_color()I74
+Ea||D5G2;|pin@5||B
+Eb||D5G2;|pin@4||B
+X
+
+# Cell wire40;1{sch}
+Cwire40;1{sch}||schematic|1083965121000|1244505276447||ATTR_L(D5G1;HNOLPUDX-20.5;Y-6.5;)S100|ATTR_LEWIRE(D5G1;HNPTX-20.5;Y-9.5;)I1|ATTR_layer(D5FLeave alone;G1;HNOLPX-20.5;Y-7.5;)S2|ATTR_width(D5FLeave alone;G1;HNOLPX-20.5;Y-8.5;)S7|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-23|-1||||
+NOff-Page|conn@1||-5.5|-1|||YRR|
+Ngeneric:Invisible-Pin|pin@0||-4|6|||||ART_message(BD5G2;)Swire40
+Ngeneric:Invisible-Pin|pin@1||7|-8|||||ART_message(D5G1;)SR = (@layer==0?15:@layer==1?0.2:@layer<8?0.15:0.02)/@width
+Ngeneric:Invisible-Pin|pin@2||7|-6|||||ART_message(D5G1;)SC = (@layer==0?0.002:@layer<8?0.002:0.003)*1e-15
+Ngeneric:Invisible-Pin|pin@3||-9|2|||||ART_message(D6G1;)S["wire in layer 'layer', 'L' lambda long,","'width' lambda wide, for the 40nm tech"]
+Ngeneric:Invisible-Pin|pin@4||-12|-14|||||ART_message(D5G1;)Scapacitance (fF/lambda)
+Ngeneric:Invisible-Pin|pin@5||3.5|-14|||||ART_message(D5G1;)Sresistance (ohm/square)
+Ngeneric:Invisible-Pin|pin@6||3.5|-17.5|||||ART_message(D5G1;)SM1 - 0.2
+Ngeneric:Invisible-Pin|pin@7||3.5|-19|||||ART_message(D5G1;)SMx : 0.15
+Ngeneric:Invisible-Pin|pin@8||3.5|-20.5|||||ART_message(D5G1;)SMz : 0.02
+Ngeneric:Invisible-Pin|pin@9||3.5|-16|||||ART_message(D5G1;)Spoly - 15
+Ngeneric:Invisible-Pin|pin@10||18|-14|||||ART_message(D5G1;)Swidth (um/lambda)
+Ngeneric:Invisible-Pin|pin@11||18|-17.5|||||ART_message(D5G1;)SM1 - 0.07/7L
+Ngeneric:Invisible-Pin|pin@12||18|-19|||||ART_message(D5G1;)SMx : 0.07/7L
+Ngeneric:Invisible-Pin|pin@13||18|-20.5|||||ART_message(D5G1;)SMz : 0.4/40L
+Ngeneric:Invisible-Pin|pin@14||18|-16|||||ART_message(D5G1;)Spoly - 0.04/4L
+Ngeneric:Invisible-Pin|pin@15||-12|-17.5|||||ART_message(D5G1;)SM1 - 0.0021 or 0.21fF/um
+Ngeneric:Invisible-Pin|pin@17||-12|-20.5|||||ART_message(D5G1;)SMz : 0.003 or 0.3fF/um
+Ngeneric:Invisible-Pin|pin@18||-12|-16|||||ART_message(D5G1;)Spoly - 0.002 or 0.2fF/um
+Ngeneric:Invisible-Pin|pin@19||-12|-19|||||ART_message(D5G1;)SMx - 0.002 or 0.2fF/um
+Iwire40;1{ic}|wire90@1||14|7.88|||D0G4;|ATTR_L(D5FLeave alone;G1;OLPUD)S100|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NOLPY-1;)S2|ATTR_width(D5FLeave alone;G1;NOLPY-2;)S7
+Iwire;1{ic}|wire@0||-15|-1|||D0G4;|ATTR_C(D5G1;NOLPUCY-2.5;)S(@layer==0?0.002:@layer<8?0.002:0.003)*1e-15|ATTR_L(D5FLeave alone;G1;OLPUD)S@L|ATTR_R(D5G1;NOLPURY-1.5;)S(@layer==0?15:@layer==1?0.2:@layer<8?0.151:0.02)/@width
+Awire|net@0|||0|wire@0|a|-19|-1|conn@0|y|-21|-1
+Awire|net@1|||1800|wire@0|b|-11|-1|conn@1|y|-7.5|-1
+Ea||D4G2;|conn@0|a|B
+Eb||D4G2;|conn@1|a|B
+X