migrate jelib->delib
[fleet.git] / chips / omegaCounter / 40nm / electric / purpleFive.delib / inv2iLT.sch
diff --git a/chips/omegaCounter/40nm/electric/purpleFive.delib/inv2iLT.sch b/chips/omegaCounter/40nm/electric/purpleFive.delib/inv2iLT.sch
new file mode 100644 (file)
index 0000000..b575751
--- /dev/null
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+HpurpleFive|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell inv2iLT;2{sch}
+Cinv2iLT;2{sch}||schematic|1021415734000|1159375635930||ATTR_Delay(D5G1;HNPX-11.5;Y-8.5;)I100|ATTR_LEGATE(D5G1;HNPTX-11.5;Y-13.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-12;Y-9.5;)I-1|ATTR_X(D5G1;HNOJPX-11.5;Y-7.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-11.5;Y-11.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-11.5;Y-12.5;)Sstrong1|ATTR_su(D5G1;HNPTX-11.5;Y-10.5;)I-1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-10|-1|||Y|
+NOff-Page|conn@1||-10|1|||Y|
+NOff-Page|conn@2||12.5|0||||
+IredFive:inv2iLT;1{ic}|inv2iLT@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
+Iinv2iLT;2{ic}|inv2iLT@1||21|10|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
+Ngeneric:Invisible-Pin|pin@0||16|-12.5|||||ART_message(D5G2;)S[X is drive strength,N drive strength is twice P strength]
+Ngeneric:Invisible-Pin|pin@1||0.5|11.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 2]
+Ngeneric:Invisible-Pin|pin@2||-3.5|16|||||ART_message(D5G2;)S[two-input LO-threshold inverter]
+Ngeneric:Invisible-Pin|pin@3||0.5|18.5|||||ART_message(D5G6;)S[inv2iLT]
+Awire|net@0|||0|inv2iLT@0|in[n]|-2.5|-1|conn@0|y|-8|-1
+Awire|net@1|||0|inv2iLT@0|in[p]|-2.5|1|conn@1|y|-8|1
+Awire|net@2|||0|conn@2|a|10.5|0|inv2iLT@0|out|2.5|0
+Ein[n]||D5G2;|conn@0|a|I|ATTR_le(D5G1;NY2.5;)F0.67
+Ein[p]||D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F0.67
+Eout||D5G2;|conn@2|y|O|ATTR_le(D5G1;NY2;)F1.33
+X