migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / purpleFive.delib / nand2PH.sch

diff --git a/chips/omegaCounter/40nm/electric/purpleFive.delib/nand2PH.sch b/chips/omegaCounter/40nm/electric/purpleFive.delib/nand2PH.sch
new file mode 100644 (file)
index 0000000..ff1665e
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/purpleFive.delib/nand2PH.sch
@@ -0,0 +1,61 @@
+HpurpleFive|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell nand2PH;1{sch}
+Cnand2PH;1{sch}||schematic|1021415734000|1248729331835||ATTR_Delay(D5G1;HNPX-15.5;Y-14.5;)I100|ATTR_LEGATE(D5G1;HNPTX-15.5;Y-18.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-15.5;Y-13.5;)I-1|ATTR_X(D5G1;HNOJPX-15.5;Y-12.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-15.5;Y-16.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-15.5;Y-17.5;)Sstrong1|ATTR_su(D5G1;HNPTX-15.5;Y-15.5;)I-1|prototype_center()I[0,0]
+IredFive:NMOS;1{ic}|NMOS@1||1|-10|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
+IredFive:NMOS;1{ic}|NMOS@2||6|-3|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/10.
+IredFive:NMOS;1{ic}|NMOS@3||-5|-3|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/10.
+IredFive:PMOS;1{ic}|PMOS@2||6|6|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
+IredFive:PMOS;1{ic}|PMOS@3||-5|6|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||14.5|6|||YRR|
+NOff-Page|conn@1||19.5|1|||Y|
+NOff-Page|conn@2||-13.5|6||||
+NOff-Page|conn@3||-15|-10||||
+NGround|gnd@0||1|-16||||
+NGround|gnd@1||-5|-7||||
+NGround|gnd@2||6|-7||||
+Inand2PH;1{ic}|nand2PH@0||26.75|14|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2.5;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.5;Y2.5;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
+Ngeneric:Invisible-Pin|pin@0||-2|16|||||ART_message(D5G2;)S[PH is Pulse High - This is a pulse control logic Nand,that has a high-going pulsed output,(inputs are low-going pulses)]
+Ngeneric:Invisible-Pin|pin@1||-2|23|||||ART_message(D5G6;)S[nand2PH]
+Ngeneric:Invisible-Pin|pin@2||16|-14.5|||||ART_message(D5G2;)S[X is drive strength,One pull-up has the same strength,as the pull-down]
+NWire_Pin|pin@3||6|1||||
+NWire_Pin|pin@4||-5|1||||
+NWire_Pin|pin@5||1|1||||
+NWire_Pin|pin@6||11|-3||||
+NWire_Pin|pin@7||11|6||||
+NWire_Pin|pin@8||-10|-3||||
+NWire_Pin|pin@9||-10|6||||
+NPower|pwr@0||-5|11||||
+NPower|pwr@1||6|11||||
+Awire|net@0|||2700|NMOS@2|s|6|-5|gnd@2||6|-5
+Awire|net@1|||900|pin@3||6|1|NMOS@2|d|6|-1
+Awire|net@2|||0|pin@6||11|-3|NMOS@2|g|9|-3
+Awire|net@3|||2700|NMOS@3|s|-5|-5|gnd@1||-5|-5
+Awire|net@4|||900|pin@4||-5|1|NMOS@3|d|-5|-1
+Awire|net@5|||1800|pin@8||-10|-3|NMOS@3|g|-8|-3
+Awire|net@6|||900|NMOS@1|s|1|-12|gnd@0||1|-14
+Awire|net@7|||900|pin@5||1|1|NMOS@1|d|1|-8
+Awire|net@8|||0|NMOS@1|g|-2|-10|conn@3|y|-13|-10
+Awire|net@9|||2700|PMOS@2|s|6|8|pwr@1||6|11
+Awire|net@10|||1800|PMOS@2|g|9|6|pin@7||11|6
+Awire|net@11|||2700|pin@3||6|1|PMOS@2|d|6|4
+Awire|net@12|||2700|PMOS@3|s|-5|8|pwr@0||-5|11
+Awire|net@13|||0|PMOS@3|g|-8|6|pin@9||-10|6
+Awire|net@14|||900|PMOS@3|d|-5|4|pin@4||-5|1
+Awire|net@15|||1800|pin@3||6|1|conn@1|a|17.5|1
+Awire|net@16|||1800|pin@5||1|1|pin@3||6|1
+Awire|net@17|||1800|pin@4||-5|1|pin@5||1|1
+Awire|net@18|||1800|pin@7||11|6|conn@0|y|12.5|6
+Awire|net@19|||900|pin@7||11|6|pin@6||11|-3
+Awire|net@20|||0|pin@9||-10|6|conn@2|y|-11.5|6
+Awire|net@21|||900|pin@9||-10|6|pin@8||-10|-3
+Eina||D5G2;|conn@0|a|I|ATTR_le(D5G1;NX0.5;Y2;)F0.667
+Einb||D5G2;|conn@2|a|I|ATTR_le(D5G1;NY1.5;)F0.667
+Eout||D5G2;|conn@1|y|O|ATTR_le(D5G1;NY-1.5;)F1.67
+EresetN||D4G2;|conn@3|a|I|ATTR_le(D5G1;NX-2;Y2;)F0.333
+X