migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / purpleFive.delib / nand2PHfk.sch

diff --git a/chips/omegaCounter/40nm/electric/purpleFive.delib/nand2PHfk.sch b/chips/omegaCounter/40nm/electric/purpleFive.delib/nand2PHfk.sch
new file mode 100644 (file)
index 0000000..42ece48
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/purpleFive.delib/nand2PHfk.sch
@@ -0,0 +1,57 @@
+HpurpleFive|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell nand2PHfk;1{sch}
+Cnand2PHfk;1{sch}||schematic|1021415734000|1248729106644||ATTR_Delay(D5G1;HNPX-15.5;Y-14.5;)I100|ATTR_LEGATE(D5G1;HNPTX-15.5;Y-18.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-15.5;Y-13.5;)I-1|ATTR_X(D5G1;HNOJPX-15.5;Y-12.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-15.5;Y-16.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-15.5;Y-17.5;)Sstrong1|ATTR_su(D5G1;HNPTX-15.5;Y-15.5;)I-1|prototype_center()I[0,0]
+IredFive:NMOS;1{ic}|NMOS@1||1|-10|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
+IredFive:PMOS;1{ic}|PMOS@2||-5|6|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
+IredFive:PMOS;1{ic}|PMOS@3||6|6|YRR||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-15|-10||||
+NOff-Page|conn@1||-13.5|6||||
+NOff-Page|conn@2||25|1|||Y|
+NOff-Page|conn@3||14.5|6|||YRR|
+NGround|gnd@0||1|-16||||
+IredFive:inv;1{ic}|inv@0||15.5|-4|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invK;1{ic}|invK@0||10|-4|YRRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X/10.|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Inand2PHfk;1{ic}|nand2PHf@0||27|13.5|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2.5;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.5;Y2.5;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
+Ngeneric:Invisible-Pin|pin@0||24.5|-6|||||SIM_spice_card(D6G1;)S[.ic v(out) 0]
+NWire_Pin|pin@1||10|1||||
+NWire_Pin|pin@2||15.5|-9||||
+NWire_Pin|pin@3||10|-9||||
+NWire_Pin|pin@4||15.5|1||||
+NWire_Pin|pin@5||1|1||||
+NWire_Pin|pin@6||-5|1||||
+NWire_Pin|pin@7||6|1||||
+Ngeneric:Invisible-Pin|pin@8||16|-14.5|||||ART_message(D5G2;)S[X is drive strength,One pull-up has the same strength,as the pull-down]
+Ngeneric:Invisible-Pin|pin@9||0|26|||||ART_message(D5G6;)S[nand2PHfk]
+Ngeneric:Invisible-Pin|pin@10||0|19|||||ART_message(D5G2;)S[PH is Pulse High - This is a pulse control logic Nand,that has a high-going pulsed output,(inputs are low-going pulses),this version has a full keeper on the output]
+NPower|pwr@0||6|11||||
+NPower|pwr@1||-5|11||||
+Awire|net@0|||2700|PMOS@2|s|-5|8|pwr@1||-5|11
+Awire|net@1|||1800|conn@1|y|-11.5|6|PMOS@2|g|-8|6
+Awire|net@2|||900|PMOS@2|d|-5|4|pin@6||-5|1
+Awire|net@3|||2700|PMOS@3|s|6|8|pwr@0||6|11
+Awire|net@4|||0|conn@3|y|12.5|6|PMOS@3|g|9|6
+Awire|net@5|||2700|pin@7||6|1|PMOS@3|d|6|4
+Awire|net@6|||900|NMOS@1|s|1|-12|gnd@0||1|-14
+Awire|net@7|||900|pin@5||1|1|NMOS@1|d|1|-8
+Awire|net@8|||0|NMOS@1|g|-2|-10|conn@0|y|-13|-10
+Awire|net@9|||900|pin@4||15.5|1|inv@0|in|15.5|-1.5
+Awire|net@10|||900|inv@0|out|15.5|-6.5|pin@2||15.5|-9
+Awire|net@11|||2700|pin@3||10|-9|invK@0|in|10|-6.5
+Awire|net@12|||900|pin@1||10|1|invK@0|out|10|-1.5
+Awire|net@13|||1800|pin@7||6|1|pin@1||10|1
+Awire|net@14|||1800|pin@1||10|1|pin@4||15.5|1
+Awire|net@15|||0|pin@2||15.5|-9|pin@3||10|-9
+Awire|net@16|||1800|pin@4||15.5|1|conn@2|a|23|1
+Awire|net@17|||1800|pin@6||-5|1|pin@5||1|1
+Awire|net@18|||1800|pin@5||1|1|pin@7||6|1
+Eina||D5G2;|conn@3|a|I|ATTR_le(D5G1;NX0.5;Y2;)F0.667
+Einb||D5G2;|conn@1|a|I|ATTR_le(D5G1;NY1.5;)F0.667
+Eout||D5G2;|conn@2|y|O|ATTR_le(D5G1;NY2;)D1.67
+EresetN||D4G2;|conn@0|a|I|ATTR_le(D5G1;NX-2;Y2;)F0.333
+X