migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / purpleFive.delib / nand3.sch

diff --git a/chips/omegaCounter/40nm/electric/purpleFive.delib/nand3.sch b/chips/omegaCounter/40nm/electric/purpleFive.delib/nand3.sch
new file mode 100644 (file)
index 0000000..92a5d64
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/purpleFive.delib/nand3.sch
@@ -0,0 +1,28 @@
+HpurpleFive|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell nand3;1{sch}
+Cnand3;1{sch}||schematic|1021415734000|1159379591711||ATTR_Delay(D5G1;HNPX-14.5;Y-8;)I100|ATTR_LEGATE(D5G1;HNPTX-15;Y-13;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-14.5;Y-9;)I-1|ATTR_X(D5G1;HNOJPX-14.5;Y-7;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-14.5;Y-11;)Sstrong0|ATTR_drive1(D5G1;HNPTX-14.5;Y-12;)Sstrong1|ATTR_su(D5G1;HNPTX-14.5;Y-10;)I-1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-18|2||||
+NOff-Page|conn@1||15.5|0|||Y|
+NOff-Page|conn@2||-9|0|||Y|
+NOff-Page|conn@3||-23.5|-2||||
+IredFive:nand3;1{ic}|nand3@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX4;Y-2.5;)S@Delay|ATTR_X(D5G1.5;NOJPX3;Y2.5;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
+Inand3;1{ic}|nand3@1||27.5|19|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX3;Y2.5;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
+Ngeneric:Invisible-Pin|pin@0||30.5|-13|||||ART_message(D5G2;)S[X is drive strength,Each pull-up has the same strength,as the pull-down]
+Ngeneric:Invisible-Pin|pin@1||0|16.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 3]
+Ngeneric:Invisible-Pin|pin@2||0|19|||||ART_message(D5G2;)S["three input, fixed-size NAND"]
+Ngeneric:Invisible-Pin|pin@3||-0.5|25|||||ART_message(D5G6;)S[nand3]
+Awire|net@0|||0|nand3@0|inc|-2.5|2|conn@0|y|-16|2
+Awire|net@1|||0|nand3@0|ina|-2.5|-2|conn@3|y|-21.5|-2
+Awire|net@2|||1800|nand3@0|out|2.5|0|conn@1|a|13.5|0
+Awire|net@3|||0|nand3@0|inb|-2.5|0|conn@2|y|-7|0
+Eina||D5G2;|conn@3|a|I|ATTR_le(D5G1;NY-1.5;)F1.67
+Einb||D5G2;|conn@2|a|I|ATTR_le(D5G1;NY1.5;)F1.67
+Einc||D5G2;|conn@0|y|I|ATTR_le(D5G1;NX-1;Y-2;)F1.67
+Eout||D5G2;|conn@1|y|O|ATTR_le(D5G1;NY2;)I3
+X