migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / purpleFive.delib / nand3LTen.sch

diff --git a/chips/omegaCounter/40nm/electric/purpleFive.delib/nand3LTen.sch b/chips/omegaCounter/40nm/electric/purpleFive.delib/nand3LTen.sch
new file mode 100644 (file)
index 0000000..bfb53e7
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/purpleFive.delib/nand3LTen.sch
@@ -0,0 +1,29 @@
+HpurpleFive|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell nand3LTen;1{sch}
+Cnand3LTen;1{sch}||schematic|1021415734000|1159376004533||ATTR_Delay(D5G1;HNPX-25.5;Y-9.5;)I100|ATTR_LEGATE(D5G1;HNPTX-26;Y-14.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-25.75;Y-10.5;)I-1|ATTR_X(D5G1;HNOJPX-25.5;Y-8.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-25.5;Y-12.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-25.5;Y-13.5;)Sstrong1|ATTR_su(D5G1;HNPTX-26.5;Y-11.5;)I-1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-19.5|2||||
+NOff-Page|conn@1||12.5|0|||Y|
+NOff-Page|conn@2||-11|0|||Y|
+NOff-Page|conn@3||-22.5|-2||||
+IredFive:nand3LTen;1{ic}|nand3LTe@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX4;Y-2.5;)S@Delay|ATTR_X(D5G1.5;NOJPX3;Y2.5;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
+Inand3LTen;1{ic}|nand3LTe@1||27.5|12|||D0G4;|ATTR_Delay(D5G1;NPX4.5;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX3;Y2.5;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
+Ngeneric:Invisible-Pin|pin@0||-0.5|25|||||ART_message(D5G6;)S[nand3LTen]
+Ngeneric:Invisible-Pin|pin@1||-0.5|20|||||ART_message(D5G2;)S[one-parameter low-threshold NAND where ina is DC signal (enable)]
+Ngeneric:Invisible-Pin|pin@2||-0.5|18|||||ART_message(D5G2;)S[P to N width ratio is 2/3 to 3]
+Ngeneric:Invisible-Pin|pin@3||28|-11|||||ART_message(D5G2;)S[X is drive strength,Three pull-ups have the same strength,as the pull-down]
+Ngeneric:Invisible-Pin|pin@4||-1|15.5|||||ART_message(D5G2;)S[Sized assuming that all 3 inputs go low together]
+Awire|net@0|||0|nand3LTe@0|inc|-2.5|2|conn@0|y|-17.5|2
+Awire|net@1|||1800|conn@3|y|-20.5|-2|nand3LTe@0|ina|-2.5|-2
+Awire|net@2|||1800|nand3LTe@0|out|2.5|0|conn@1|a|10.5|0
+Awire|net@3|||0|nand3LTe@0|inb|-2.5|0|conn@2|y|-9|0
+Eina||D5G2;|conn@3|a|I|ATTR_le(D5G1;NY-1.5;)F1.033
+Einb||D5G2;|conn@2|a|I|ATTR_le(D5G1;NY1.5;)F1.33
+Einc||D5G2;|conn@0|y|I|ATTR_le(D5G1;NX-1;Y-2;)F1.33
+Eout||D5G2;|conn@1|y|O|ATTR_le(D5G1;NX0.5;Y-2.5;)I2
+X