migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / redFive.delib / inv2iLT.sch

diff --git a/chips/omegaCounter/40nm/electric/redFive.delib/inv2iLT.sch b/chips/omegaCounter/40nm/electric/redFive.delib/inv2iLT.sch
new file mode 100644 (file)
index 0000000..876a502
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/redFive.delib/inv2iLT.sch
@@ -0,0 +1,31 @@
+HredFive|8.10k
+
+# Cell inv2iLT;1{sch}
+Cinv2iLT;1{sch}||schematic|1021415734000|1248729106644||ATTR_Delay(D5G1;HNPX-12;Y-13;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-12;Y-12;)S1|ATTR_drive0(D5G1;HNPTX-12;Y-14;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-15;)Sstrong1|prototype_center()I[0,0]
+INMOS;1{ic}|NMOS@1||0|-6|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X*2.0
+IPMOS;1{ic}|PMOS@1||0|6|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-14|-6||||
+NOff-Page|conn@1||-14.5|6||||
+NOff-Page|conn@2||8|0||||
+NGround|gnd@0||0|-12.5||||
+Iinv2iLT;1{ic}|inv2iLT@0||16|10.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX1.5;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+NWire_Pin|pin@2||-3|6||||
+Ngeneric:Invisible-Pin|pin@4||25|-10|||||ART_message(D5G2;)S[X is drive strength,N drive strength is twice P strength]
+Ngeneric:Invisible-Pin|pin@5||0.5|17|||||ART_message(D5G2;)S[This is a 2 to 2 width ratio inverter]
+NWire_Pin|pin@6||0|0||||
+Ngeneric:Invisible-Pin|pin@7||0|19|||||ART_message(D5G2;)S[two-input LO-threshold inverter]
+Ngeneric:Invisible-Pin|pin@8||-1|24|||||ART_message(D5G6;)S[inv2iLT]
+NPower|pwr@0||0|12.5||||
+Awire|net@5|||1800|pin@2||-3|6|PMOS@1|g|-3|6
+Awire|net@8|||900|pwr@0||0|12.5|PMOS@1|s|0|8
+Awire|net@9|||2700|pin@6||0|0|PMOS@1|d|0|4
+Awire|net@10|||2700|gnd@0||0|-10.5|NMOS@1|s|0|-8
+Awire|net@11|||900|pin@6||0|0|NMOS@1|d|0|-4
+Awire|net@12|||0|conn@2|a|6|0|pin@6||0|0
+Awire|net@16|||1800|conn@1|y|-12.5|6|PMOS@1|g|-3|6
+Awire|net@17|||1800|conn@0|y|-12|-6|NMOS@1|g|-3|-6
+Ein[n]||D5G2;|conn@0|a|I
+Ein[p]||D5G2;|conn@1|a|I
+Eout||D5G2;|conn@2|y|O
+X