migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / redFive.delib / invCTLp.sch

diff --git a/chips/omegaCounter/40nm/electric/redFive.delib/invCTLp.sch b/chips/omegaCounter/40nm/electric/redFive.delib/invCTLp.sch
new file mode 100644 (file)
index 0000000..7bfc652
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/redFive.delib/invCTLp.sch
@@ -0,0 +1,39 @@
+HredFive|8.10k
+
+# Cell invCTLp;1{sch}
+CinvCTLp;1{sch}||schematic|993433994000|1248729232899||ATTR_Delay(D5G2;HNPX-21;Y-1;)I100|ATTR_X(D5G2;HNPX-21;Y1.5;)I1|ATTR_sloDelay(D5G2;HNPX-21;Y-3.5;)I175|prototype_center()I[0,0]
+INMOS;1{ic}|NMOS@1||0|0.5|||D0G4;|ATTR_Delay(D5G1;NOLPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
+IPMOS;1{ic}|PMOS@1||0|22|||D0G4;|ATTR_Delay(D5G1;NOLPX3.5;Y-2;)S@sloDelay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0
+IPMOS;1{ic}|PMOS@2||0|15|||D0G4;|ATTR_Delay(D5G1;NOLPX3.5;Y-2;)S@sloDelay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-13|15||||
+NOff-Page|conn@1||-12|8||||
+NOff-Page|conn@2||12.5|8||||
+NGround|gnd@0||0|-6.5||||
+IinvCTLp;1{ic}|invCTLp@0||15|27.75|||D0G4;|ATTR_Delay(D5G1;NPX4.25;Y-1.75;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I2|ATTR_sloDelay(D5G1;NPX4.75;Y-3.25;)I175
+NWire_Pin|pin@0||-5|0.5||||
+NWire_Pin|pin@1||0|20.5||||
+NWire_Pin|pin@2||-2.5|22||||
+NWire_Pin|pin@3||-5|22||||
+Ngeneric:Invisible-Pin|pin@4||0|33|||||ART_message(D5G3;)S[invCTLp]
+NWire_Pin|pin@5||0|8||||
+NWire_Pin|pin@6||-5|8||||
+NPower|pwr@0||0|28||||
+Awire|net@0|||0|PMOS@2|g|-3|15|conn@0|y|-11|15
+Awire|net@1|||2700|pin@5||0|8|PMOS@2|d|0|13
+Awire|net@2|||900|PMOS@1|d|0|20|PMOS@2|s|0|17
+Awire|net@3|||900|pin@5||0|8|NMOS@1|d|0|2.5
+Awire|net@4|||2700|pin@0||-5|0.5|pin@6||-5|8
+Awire|net@5|||900|NMOS@1|s|0|-1.5|gnd@0||0|-4.5
+Awire|net@6|||1800|pin@0||-5|0.5|NMOS@1|g|-3|0.5
+Awire|net@7|||1800|PMOS@1|g|-3|22|pin@2||-2.5|22
+Awire|net@8|||900|pwr@0||0|28|PMOS@1|s|0|24
+Awire|net@9|||2700|PMOS@1|d|0|20|pin@1||0|20.5
+Awire|net@10|||1800|pin@3||-5|22|pin@2||-2.5|22
+Awire|net@11|||900|pin@3||-5|22|pin@6||-5|8
+Awire|net@12|||1800|pin@5||0|8|conn@2|a|10.5|8|SIM_verilog_wire_type(D5G1;)Strireg
+Awire|net@13|||0|pin@6||-5|8|conn@1|y|-10|8
+Ectl||D5G2;X-4;|conn@0|y|I
+Ein||D5G2;|conn@1|a|I
+Eout||D5G2;|conn@2|y|O
+X