migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / redFive.delib / nand2HTen.sch

diff --git a/chips/omegaCounter/40nm/electric/redFive.delib/nand2HTen.sch b/chips/omegaCounter/40nm/electric/redFive.delib/nand2HTen.sch
new file mode 100644 (file)
index 0000000..1368cf7
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/redFive.delib/nand2HTen.sch
@@ -0,0 +1,53 @@
+HredFive|8.10k
+
+# Cell nand2HTen;1{sch}
+Cnand2HTen;1{sch}||schematic|1021415734000|1248729055117||ATTR_Delay(D5G1;HNPX-16.5;Y-7;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-16.5;Y-6;)S1|ATTR_drive0(D5G1;HNPTX-16.5;Y-8;)Sstrong0|ATTR_drive1(D5G1;HNPTX-16.5;Y-9;)Sstrong1|ATTR_verilog_template(D5G1;NTX6;Y-17.5;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
+IPMOS;1{ic}|PMOS@2||4.5|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S2.*@X
+IPMOS;1{ic}|PMOS@3||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOLPX3.5;Y0.5;)Smax(@X/5., 5./6.)
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||21|0|||Y|
+NOff-Page|conn@1||16.5|-5|||RR|
+NOff-Page|conn@2||-14|-1||||
+Inand2HTen;1{ic}|nand2HTe@0||30|13|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.5;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_LEGATE(T)I1|ATTR_LEPARALLGRP()I-1|ATTR_su(T)I-1
+Inms2b;1{ic}|nms2@0||0|-9|||D0G4;|ATTR_Delay(D5G1;NOJPX3;Y-0.5;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-2.25;Y1.5;)S@X|ATTR_LEGATE(OJT)S@LEGATE|ATTR_LEPARALLGRP(T)I-1
+NWire_Pin|pin@0||-9|-9||||
+Ngeneric:Invisible-Pin|pin@1||9|6|||||ART_message(D5G1;)S[fixed size]
+Ngeneric:Invisible-Pin|pin@2||0.5|25|||||ART_message(D5G6;)S[nand2HTen]
+NWire_Pin|pin@3||9|-5||||
+NWire_Pin|pin@4||9|4||||
+NWire_Pin|pin@5||4.5|0||||
+NWire_Pin|pin@6||-9|-1||||
+Ngeneric:Invisible-Pin|pin@7||-0.5|20|||||ART_message(D5G2;)S[one-parameter high-threshold NAND where ina is enable (DC) input]
+NWire_Pin|pin@8||-5|0||||
+NWire_Pin|pin@9||0|0||||
+NWire_Pin|pin@10||-9|4||||
+Ngeneric:Invisible-Pin|pin@11||-0.5|17.5|||||ART_message(D5G2;)S[P to N width ratio is 4 to 2]
+Ngeneric:Invisible-Pin|pin@12||31.5|-12.5|||||ART_message(D5G2;)S[X is drive strength,Pull-up has twice the strength,of the pull-down]
+NWire_Pin|pin@13||4.5|8||||
+NWire_Pin|pin@14||-5|8||||
+NWire_Pin|pin@15||0|8||||
+NPower|pwr@0||0|11.5||||
+Awire|net@0|||2700|pin@0||-9|-9|pin@6||-9|-1
+Awire|net@1|||1800|pin@3||9|-5|conn@1|y|14.5|-5
+Awire|net@2|||2700|pin@3||9|-5|pin@4||9|4
+Awire|net@3|||0|pin@6||-9|-1|conn@2|y|-12|-1
+Awire|net@4|||0|pin@9||0|0|pin@8||-5|0
+Awire|net@5|||0|pin@5||4.5|0|pin@9||0|0
+Awire|net@6|||900|pin@9||0|0|nms2@0|d|0|-3
+Awire|net@7|||2700|pin@6||-9|-1|pin@10||-9|4
+Awire|net@8|||0|pin@4||9|4|PMOS@2|g|7.5|4
+Awire|net@9|||2700|pin@5||4.5|0|PMOS@2|d|4.5|2
+Awire|net@10|||2700|pin@8||-5|0|PMOS@3|d|-5|2
+Awire|net@11|||1800|pin@10||-9|4|PMOS@3|g|-8|4
+Awire|net@12|||900|pin@13||4.5|8|PMOS@2|s|4.5|6
+Awire|net@13|||2700|PMOS@3|s|-5|6|pin@14||-5|8
+Awire|net@14|||1800|pin@5||4.5|0|conn@0|a|19|0
+Awire|net@15|||1800|pin@15||0|8|pin@13||4.5|8
+Awire|net@16|||1800|pin@14||-5|8|pin@15||0|8
+Awire|net@17|||2700|pin@15||0|8|pwr@0||0|11.5
+Awire|net@18|||1800|nms2@0|g2|3|-5|pin@3||9|-5
+Awire|net@19|||0|nms2@0|g|-3|-9|pin@0||-9|-9
+Eina||D5G2;|conn@2|a|I
+Einb||D5G2;|conn@1|a|I
+Eout||D5G2;|conn@0|y|O
+X