migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / redFive.delib / nand2en_3n.sch

diff --git a/chips/omegaCounter/40nm/electric/redFive.delib/nand2en_3n.sch b/chips/omegaCounter/40nm/electric/redFive.delib/nand2en_3n.sch
new file mode 100644 (file)
index 0000000..d312e2f
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/redFive.delib/nand2en_3n.sch
@@ -0,0 +1,59 @@
+HredFive|8.10k
+
+# Cell nand2en_3n;1{sch}
+Cnand2en_3n;1{sch}||schematic|1021415734000|1248729055117||ATTR_Delay(D5G1;HNPX-20;Y-5.5;)I100|ATTR_X(D5G1;HNPX-20;Y-4.5;)I1|ATTR_drive0(D5G1;HNPTX-20;Y-6.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-20;Y-7.5;)Sstrong1|ATTR_verilog_template(D5G1;NTX25.5;Y-14;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
+IPMOS;1{ic}|PMOS@2||5.5|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
+IPMOS;1{ic}|PMOS@3||-9|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)SMath.max(((Number)@X).doubleValue()/10., 5./6.)
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||15|0||||
+NOff-Page|conn@1||15|-5|||RR|
+NOff-Page|conn@2||-18|-1||||
+Inand2en_3n;1{ic}|nand2en_@0||25|12.5|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Inms2b;1{ic}|nms2@0||-2|-9|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S@X/3.
+Inms2b;1{ic}|nms2@1||5.5|-9|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S@X/3.
+Inms2b;1{ic}|nms2@2||-9|-9|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S@X/3.
+NWire_Pin|pin@0||-2|0||||
+Ngeneric:Invisible-Pin|pin@1||-0.5|15|||||ART_message(D5G2;)S[3 n-stacks for larger sizes]
+NWire_Pin|pin@2||5.5|7.5||||
+NWire_Pin|pin@3||-9|7.5||||
+Ngeneric:Invisible-Pin|pin@4||-0.5|25|||||ART_message(D5G6;)S[nand2en_3n]
+NWire_Pin|pin@5||10|-5||||
+NWire_Pin|pin@6||10|4||||
+NWire_Pin|pin@7||-13|-1||||
+Ngeneric:Invisible-Pin|pin@8||-0.5|20|||||ART_message(D5G2;)S[one-parameter NAND where ina is DC signal (enable)]
+NWire_Pin|pin@9||-9|0||||
+NWire_Pin|pin@10||-13|4||||
+Ngeneric:Invisible-Pin|pin@11||-0.5|17.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 2 (2/10 for enable input)]
+Ngeneric:Invisible-Pin|pin@12||31.5|-8|||||ART_message(D5G2;)S[X is drive strength,One pull-up has the same strength,as the pull-down]
+NWire_Pin|pin@13||-13|-9||||
+NWire_Pin|pin@14||5.5|0||||
+NPower|pwr@0||-9|10.5||||
+Awire|net@0|||2700|nms2@1|d|5.5|-3|pin@14||5.5|0
+Awire|net@1|||1800|nms2@1|g2|8.5|-5|pin@5||10|-5
+Awire|net@2|||1800|nms2@0|g2|1|-5|nms2@1|g2|8.5|-5
+Awire|net@3|||900|pin@0||-2|0|nms2@0|d|-2|-3
+Awire|net@4|||0|pin@14||5.5|0|pin@0||-2|0
+Awire|net@5|||0|pin@0||-2|0|pin@9||-9|0
+Awire|net@6|||1800|nms2@2|g2|-6|-5|nms2@0|g2|1|-5
+Awire|net@7|||0|nms2@1|g|2.5|-9|nms2@0|g|-5|-9
+Awire|net@8|||1800|nms2@2|g|-12|-9|nms2@0|g|-5|-9
+Awire|net@9|||900|pin@9||-9|0|nms2@2|d|-9|-3
+Awire|net@10|||2700|pin@3||-9|7.5|pwr@0||-9|10.5
+Awire|net@11|||0|pin@2||5.5|7.5|pin@3||-9|7.5
+Awire|net@12|||1800|pin@5||10|-5|conn@1|y|13|-5
+Awire|net@13|||2700|pin@5||10|-5|pin@6||10|4
+Awire|net@14|||0|pin@7||-13|-1|conn@2|y|-16|-1
+Awire|net@15|||2700|pin@7||-13|-1|pin@10||-13|4
+Awire|net@16|||2700|pin@13||-13|-9|pin@7||-13|-1
+Awire|net@17|||1800|pin@13||-13|-9|nms2@2|g|-12|-9
+Awire|net@18|||0|conn@0|a|13|0|pin@14||5.5|0
+Awire|net@19|||2700|pin@14||5.5|0|PMOS@2|d|5.5|2
+Awire|net@20|||0|pin@6||10|4|PMOS@2|g|8.5|4
+Awire|net@21|||900|pin@2||5.5|7.5|PMOS@2|s|5.5|6
+Awire|net@22|||2700|pin@9||-9|0|PMOS@3|d|-9|2
+Awire|net@23|||1800|pin@10||-13|4|PMOS@3|g|-12|4
+Awire|net@24|||900|pin@3||-9|7.5|PMOS@3|s|-9|6
+Eina||D5G2;|conn@2|a|I
+Einb||D5G2;|conn@1|a|I
+Eout||D5G2;|conn@0|y|O
+X