migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / redFive.delib / nand3en.sch

diff --git a/chips/omegaCounter/40nm/electric/redFive.delib/nand3en.sch b/chips/omegaCounter/40nm/electric/redFive.delib/nand3en.sch
new file mode 100644 (file)
index 0000000..c99b50b
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/redFive.delib/nand3en.sch
@@ -0,0 +1,65 @@
+HredFive|8.10k
+
+# Cell nand3en;1{sch}
+Cnand3en;1{sch}||schematic|1021415734000|1248729055117||ATTR_Delay(D5G1;HNPX-29;Y-7;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-29;Y-6;)S1|ATTR_drive0(D5G1;HNPTX-29;Y-8;)Sstrong0|ATTR_drive1(D5G1;HNPTX-29;Y-9;)Sstrong1|ATTR_verilog_template(D5G1;NTX20.5;Y-17.5;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb), $(inc));|prototype_center()I[0,0]
+IPMOS;1{ic}|PMOS@3||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOLPX2;Y2;)Smax(@X/10., 5./6.)
+IPMOS;1{ic}|PMOS@4||4.5|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
+IPMOS;1{ic}|PMOS@5||-14|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-22|4||||
+NOff-Page|conn@1||0|14.5|||R|
+NOff-Page|conn@2||14|-1|||RR|
+NOff-Page|conn@3||-15|-12||||
+Inand3en;1{ic}|nand3en@0||29|14|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Inms3;1{ic}|nms3@0||0|-12|||D0G4;|ATTR_Delay(D5G1;NOJPX3;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-2;Y0.5;)S@X
+NWire_Pin|pin@0||9|-8||||
+NWire_Pin|pin@1||-18|-4||||
+NWire_Pin|pin@2||-18|4||||
+NWire_Pin|pin@3||-14|0||||
+Ngeneric:Invisible-Pin|pin@4||-0.5|27|||||ART_message(D5G6;)S[nand3en]
+NWire_Pin|pin@5||9|-1||||
+NWire_Pin|pin@6||9|4||||
+NWire_Pin|pin@7||4.5|0||||
+NWire_Pin|pin@8||-9|-12||||
+Ngeneric:Invisible-Pin|pin@9||-0.5|22|||||ART_message(D5G2;)S["three input, fixed-size NAND where ina is DC signal (enable)"]
+NWire_Pin|pin@10||-5|0||||
+NWire_Pin|pin@11||0|0||||
+NWire_Pin|pin@12||-9|4||||
+Ngeneric:Invisible-Pin|pin@13||-0.5|19.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 3]
+Ngeneric:Invisible-Pin|pin@14||30|-10|||||ART_message(D5G2;)S[X is drive strength,Each pull-up has the same strength,as the pull-down]
+NWire_Pin|pin@15||4.5|7.5||||
+NWire_Pin|pin@16||-14|7.5||||
+NWire_Pin|pin@17||-5|7.5||||
+NPower|pwr@0||-5|11.5||||
+Awire|net@0|||900|pin@17||-5|7.5|PMOS@3|s|-5|6
+Awire|net@1|||1800|pin@12||-9|4|PMOS@3|g|-8|4
+Awire|net@2|||2700|pin@10||-5|0|PMOS@3|d|-5|2
+Awire|net@3|||1800|pin@8||-9|-12|nms3@0|g|-3|-12
+Awire|net@4|||900|pin@5||9|-1|pin@0||9|-8
+Awire|net@5|||0|pin@0||9|-8|nms3@0|g2|3|-8
+Awire|net@6|||0|nms3@0|g3|-3|-4|pin@1||-18|-4
+Awire|net@7|||2700|pin@1||-18|-4|pin@2||-18|4
+Awire|net@8|||0|pin@2||-18|4|conn@0|y|-20|4
+Awire|net@9|||0|pin@10||-5|0|pin@3||-14|0
+Awire|net@10|||900|pin@11||0|0|nms3@0|d|0|-2
+Awire|net@11|||1800|pin@5||9|-1|conn@2|y|12|-1
+Awire|net@12|||2700|pin@5||9|-1|pin@6||9|4
+Awire|net@13|||0|pin@8||-9|-12|conn@3|y|-13|-12
+Awire|net@14|||0|pin@11||0|0|pin@10||-5|0
+Awire|net@15|||0|pin@7||4.5|0|pin@11||0|0
+Awire|net@16|||2700|pin@11||0|0|conn@1|a|0|12.5
+Awire|net@17|||2700|pin@8||-9|-12|pin@12||-9|4
+Awire|net@18|||2700|pin@7||4.5|0|PMOS@4|d|4.5|2
+Awire|net@19|||1800|PMOS@4|g|7.5|4|pin@6||9|4
+Awire|net@20|||2700|pin@3||-14|0|PMOS@5|d|-14|2
+Awire|net@21|||0|PMOS@5|g|-17|4|pin@2||-18|4
+Awire|net@22|||900|pin@15||4.5|7.5|PMOS@4|s|4.5|6
+Awire|net@23|||2700|PMOS@5|s|-14|6|pin@16||-14|7.5
+Awire|net@24|||1800|pin@17||-5|7.5|pin@15||4.5|7.5
+Awire|net@25|||1800|pin@16||-14|7.5|pin@17||-5|7.5
+Awire|net@26|||2700|pin@17||-5|7.5|pwr@0||-5|11.5
+Eina||D5G2;|conn@3|a|I
+Einb||D5G2;|conn@2|a|I
+Einc||D5G2;|conn@0|y|I
+Eout||D5G2;|conn@1|y|O
+X