added "mem" ship

[fleet.git] / contrib / demo.fleet

diff --git a/contrib/demo.fleet b/contrib/demo.fleet
index 64810b1..bead521 100644 (file)
--- a/contrib/demo.fleet
+++ b/contrib/demo.fleet
@@ -1,24 +1,38 @@
 #include "contrib/demo.ships"
 
-debug.data: [*] take, deliver;
+// values and addresses to write
+1: sendto mem.write_addr;
+2: sendto mem.write_addr;
+3: sendto mem.write_addr;
+9: sendto mem.write_data;
+8: sendto mem.write_data;
+7: sendto mem.write_data;
 
-1:       sendto alu2.a;
-1:        sendto alu2.b;
-0:        sendto alu2.op;
-0:        sendto alu2.op;
-0:        sendto alu2.op;
-0:        sendto alu2.op;
+// memory write ports accept the values
+mem.write_addr:  [*] take, deliver;
+mem.write_data:  [*] take, deliver;
 
-alu2.out:
-   take;
-   [2]   sendto alu2.a;
-   [2]   sendto alu2.b;
-   take, sendto alu2.a;
-   take, sendto alu2.b;
-   take, sendto debug.data;
+// once all three are written, cue the fifo
+mem.write_done:
+  [3] take;
+  ack fifo.out;
 
-alu2.op: [*] take, deliver;
-alu2.a:  [*] take, deliver;
-alu2.b:  [*] take, deliver;
+// meanwhile, the fifo is sitting on a set of read addresses
+fifo.in: [*] take, deliver;
+1: sendto fifo.in;
+2: sendto fifo.in;
+3: sendto fifo.in;
+1: sendto fifo.in;
+1: sendto fifo.in;
+1: sendto fifo.in;
 
+// when it gets the ack, it issues them all to the memory read unit
+fifo.out:
+  wait;
+  [*] take, sendto mem.read_addr;
+
+// values read from memory go to debug (which accepts them)
+mem.read_addr:   [*] take, deliver;
+mem.read_data:   [*] take, sendto debug.data;
+debug.data:      [*] take, deliver;