works (again)

[fleet.git] / electric / arbiterM.jelib

diff --git a/electric/arbiterM.jelib b/electric/arbiterM.jelib
index ec1ecd0..68d8957 100755 (executable)
--- a/electric/arbiterM.jelib
+++ b/electric/arbiterM.jelib
@@ -100,7 +100,7 @@ Ereq[B]||D5G2;|pin@1||I
 X
 
 # Cell arbiter2;1{lay}
-Carbiter2;1{lay}||cmos90|1188748831546|1239323507907||ATTR_NCC(D5G3;NTY140;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1239323608616
+Carbiter2;1{lay}||cmos90|1188748831546|1241981698008||ATTR_NCC(D5G3;NTY140;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981714344
 Ihalf2inArb;1{lay}|halfArb@4||0|-72|||D5G4;
 Ihalf2inArb;1{lay}|halfArb@5||0|72|Y||D5G4;
 NMetal-1-Pin|pin@44||6|4||||
@@ -559,7 +559,7 @@ Ereq[B]||D5G2;|pin@2||I
 X
 
 # Cell half2inArb;1{lay}
-Chalf2inArb;1{lay}||cmos90|1188745231728|1239323507907||ATTR_NCC(D5G3;NTX-8;Y70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1239323608616
+Chalf2inArb;1{lay}||cmos90|1188745231728|1241981698008||ATTR_NCC(D5G3;NTX-8;Y70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981714344
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NMetal-1-P-Active-Con|contact@62||31|-50||20.8|Y|
 NMetal-1-P-Active-Con|contact@66||39|-50||20.8|Y|
@@ -813,7 +813,7 @@ Evdd_3||D5G2;|pinsVddG@3|vdd_1|P
 X
 
 # Cell half2inArb;1{sch}
-Chalf2inArb;1{sch}||schematic|1188747897929|1231519946316|
+Chalf2inArb;1{sch}||schematic|1188747897929|1240453455444|
 IorangeTSMC090nm:PMOSx;1{ic}|NMOSx@0||11|-7.5|Y||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S10
 IorangeTSMC090nm:NMOSx;1{ic}|PMOSx@0||11|-18.5|Y||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S10
 Ngeneric:Facet-Center|art@0||0|0||||AV
@@ -842,7 +842,7 @@ Awire|net@26|||1800|pin@8||3|-24|pin@17||11|-24
 Awire|net@27|||2700|pin@17||11|-24|PMOSx@0|d|11|-20.5
 Awire|net@30|||0|PMOSx@0|g|8|-18.5|pin@18||-9|-18.5
 Awire|net@31|||900|conn@0|y|-9|-14.5|pin@18||-9|-18.5
-Awire|net@32|||900|pin@19||11|-13|PMOSx@0|s|11|-16.5
+Awire|net@32|||900|pin@19||11|-13|PMOSx@0|s|11|-16.5|SIM_verilog_wire_type(D5G2;)Strireg
 Awire|net@34|||900|NMOSx@0|s|11|-9.5|pin@19||11|-13
 Awire|net@35|||0|conn@1|a|14|-13|pin@19||11|-13
 Awire|net@37|||2700|pin@8||3|-24|conn@3|a|3|-14