adding Alex's ESD experiment to top level

[fleet.git] / electric / esdTest.jelib

diff --git a/electric/esdTest.jelib b/electric/esdTest.jelib
index c1f42ae..365a786 100644 (file)
--- a/electric/esdTest.jelib
+++ b/electric/esdTest.jelib
@@ -1,5 +1,5 @@
 # header information:
-HesdTest|8.09j
+HesdTest|8.09k
 
 # Views:
 Vicon|ic
@@ -28,33 +28,33 @@ Tnmos|CapacitanceParasiticForDiffusionINnmos()D0.10000000149011612|CapacitancePa
 Trcmos|ScaleFORrcmos()D1000.0
 
 # Cell esdTopFilled;1{ic}
-CesdTopFilled;1{ic}||artwork|1243544400420|1243544400423|E
+CesdTopFilled;1{ic}||artwork|1243544400420|1243586774777|E
 Ngeneric:Facet-Center|art@0||0|0||||AV
-NOpened-Thicker-Polygon|art@1||0|0|6|10|||SCHEM_function(D5G2;)SesdTopFilled|trace()V[-3/-5,-3/5,3/5,3/-5,-3/-5]
-Nschematic:Bus_Pin|pin@0||2|7||||
-Nschematic:Wire_Pin|pin@1||2|5||||
-Nschematic:Bus_Pin|pin@2||-5|0||||
-Ngeneric:Invisible-Pin|pin@3||-3|0|1|1||
-Nschematic:Bus_Pin|pin@4||5|0||||
-Ngeneric:Invisible-Pin|pin@5||3|0|1|1||
+NOpened-Thicker-Polygon|art@1||0|0|8|10|||SCHEM_function(D5G2;)SesdTopFilled|trace()V[-4/-5,-4/5,4/5,4/-5,-4/-5]
+Nschematic:Bus_Pin|pin@0||3|7||||
+Nschematic:Wire_Pin|pin@1||3|5||||
+Nschematic:Bus_Pin|pin@2||-6|0||||
+Ngeneric:Invisible-Pin|pin@3||-4|0|1|1||
+Nschematic:Bus_Pin|pin@4||6|0||||
+Ngeneric:Invisible-Pin|pin@5||4|0|1|1||
 Nschematic:Bus_Pin|pin@6||0|7||||
 Nschematic:Wire_Pin|pin@7||0|5||||
-Nschematic:Bus_Pin|pin@8||-2|7||||
-Nschematic:Wire_Pin|pin@9||-2|5||||
-Aschematic:wire|net@0|||2700|pin@1||2|5|pin@0||2|7
-Aschematic:bus|net@1|||IJ0|pin@3||-3|0|pin@2||-5|0
-Aschematic:bus|net@2|||IJ1800|pin@5||3|0|pin@4||5|0
+Nschematic:Bus_Pin|pin@10||-3|7||||
+Nschematic:Wire_Pin|pin@11||-3|5||||
+Aschematic:wire|net@0|||2700|pin@1||3|5|pin@0||3|7
+Aschematic:bus|net@1|||IJ0|pin@3||-4|0|pin@2||-6|0
+Aschematic:bus|net@2|||IJ1800|pin@5||4|0|pin@4||6|0
 Aschematic:wire|net@3|||2700|pin@7||0|5|pin@6||0|7
-Aschematic:wire|net@4|||2700|pin@9||-2|5|pin@8||-2|7
+Aschematic:wire|net@5|||2700|pin@11||-3|5|pin@10||-3|7
 Egnd||D5G2;|pin@0||B
 Ein[0:2]||D5G2;|pin@2||I
 Eout[0:2]||D5G2;|pin@4||O
 Evdd||D5G2;|pin@6||B
-Evdd18||D5G2;|pin@8||B
+EvddAlex||D5G2;|pin@10||I
 X
 
 # Cell esdTopFilled;1{lay}
-CesdTopFilled;1{lay}||cmos90|1239558882952|1243545709281|
+CesdTopFilled;1{lay}||cmos90|1239558882952|1243586905416|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 IfillM:fillAll1x9vdd;1{lay}|fillAll1@6||-4896|-5616|||D5G4;
 IfillM:fillAll1x9vdd;1{lay}|fillAll1@7||-3456|-5616|||D5G4;
@@ -1788,6 +1788,7 @@ Egnd_1479||D5G5;|fillAll9@251|gnd_7|G
 Egnd_1480||D5G5;|fillAll9@254|gnd_5|G
 Egnd_1481||D5G5;|fillAll9@254|gnd_7|G
 Evdd||D5G5;|fillAll1@40|vdd|P
+EvddAlex||D5G25;|top@1|vdd|I
 Evdd_1||D5G5;|fillAll1@6|vdd_1|P
 Evdd_2||D5G5;|fillAll1@40|vdd_2|P
 Evdd_3||D5G5;|fillAll1@6|vdd_3|P
@@ -2916,26 +2917,34 @@ Evdd_1487||D5G5;|fillAll9@254|vdd_23|P
 X
 
 # Cell esdTopFilled;1{sch}
-CesdTopFilled;1{sch}||schematic|1243544323286|1243545911814|
+CesdTopFilled;1{sch}||schematic|1243544323286|1243586716447|
 Ngeneric:Facet-Center|art@0||0|0||||AV
-NOff-Page|conn@0||2.5|16.5|||R|
-NOff-Page|conn@1||-1.5|16.5|||R|
-NOff-Page|conn@2||0.5|18|||R|
+NOff-Page|conn@0||35.5|16.5|||R|
+NOff-Page|conn@2||33.5|18|||R|
 NOff-Page|conn@3||-8.5|4||||
 NOff-Page|conn@4||10.5|4||||
+NGlobal-Partition|conn@5||0.5|21.5||||
 IesdTopFilled;1{ic}|esdTopFi@0||22.5|19.5|||D5G4;
 IfillM:fillCap;1{ic}|fillCap[1:6786]|D5G1;|33.5|4.5|||D5G4;
+NWire_Pin|pin@0||-1.5|18||||
+Ngeneric:Invisible-Pin|pin@1||-11|15|||||ART_message(D5G1;)S[This vdd18 is NOT connected,to the one for the marina,"padframe, so it is not",exported above this level]
+Ngeneric:Invisible-Pin|pin@2||33|-4|||||ART_message(D5G1;)S[This fillCap iS connected,to the rest of the fill in the,"core, so the vdd/gnd ports",are what really goes here]
+NWire_Pin|pin@3||35.5|11||||
+NWire_Pin|pin@4||33.5|11||||
+NWire_Pin|pin@5||2.5|18||||
 Itop;1{ic}|top@0||0.5|4|||D5G4;
-Awire|net@0|||900|conn@2|a|0.5|16|top@0|vdd|0.5|11
-Awire|net@1|||900|conn@1|a|-1.5|14.5|top@0|vdd18|-1.5|11
-Awire|net@2|||900|conn@0|a|2.5|14.5|top@0|gnd|2.5|11
+Awire|gnd|D5G1;||2700|top@0|gnd|2.5|11|pin@5||2.5|18
 Abus|net@3|||IJ0|conn@4|a|8.5|4|top@0|out[0:2]|5.5|4
 Abus|net@4|||IJ1800|conn@3|y|-6.5|4|top@0|in[0:2]|-4.5|4
+Awire|net@6|||900|conn@0|a|35.5|14.5|pin@3||35.5|11
+Awire|net@7|||900|conn@2|a|33.5|16|pin@4||33.5|11
+Awire|net@9|||900|conn@5|bottom|0.5|20.5|top@0|vdd|0.5|11
+Awire|vdd18|D5G1;||2700|top@0|vdd18|-1.5|11|pin@0||-1.5|18
 Egnd||D5G2;X1;|conn@0|y|B
 Ein[0:2]||D5G2;X-8;|conn@3|y|I
 Eout[0:2]||D5G2;X4.5;|conn@4|y|O
 Evdd||D5G2;X2;|conn@2|y|B
-Evdd18||D5G2;X1;|conn@1|y|B
+EvddAlex||D5G2;|conn@5|top|I
 X
 
 # Cell fork_halfUm;1{lay}