works speculatively with predCond3

[fleet.git] / electric / latchesK.jelib

diff --git a/electric/latchesK.jelib b/electric/latchesK.jelib
index 8e4d9ed..b45d598 100755 (executable)
--- a/electric/latchesK.jelib
+++ b/electric/latchesK.jelib
@@ -348,7 +348,7 @@ Eout[1]||D5G2;|pin@4||O
 X
 
 # Cell latch1in10A;1{lay}
-Clatch1in10A;1{lay}||cmos90|1194236252807|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
+Clatch1in10A;1{lay}||cmos90|1194236252807|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1243983951396
 Ngeneric:Facet-Center|art@0||0|0||||AV
 Iraw1inLatchF;1{lay}|hi1inLat@0||0|0|||D5G4;
 IlatchPartsK:latchAmp10;1{lay}|latchAmp@0||25|0|||D5G4;
@@ -3813,7 +3813,7 @@ Eout|out[1]|D5G2;|pin@2||O
 X
 
 # Cell mlat1in5s;2{lay}
-Cmlat1in5s;2{lay}||cmos90|1204972178946|1243362431039||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981714344
+Cmlat1in5s;2{lay}||cmos90|1204972178946|1243362431039||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1244052682608
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NMetal-1-P-Active-Con|contact@0||5.5|-46.5||20.8|X|
 NMetal-1-N-Active-Con|contact@1||7.5|0||20.8|X|
@@ -5569,7 +5569,7 @@ Eout[1]||D5G2;|pin@8||O
 X
 
 # Cell mlat2in5s;1{lay}
-Cmlat2in5s;1{lay}||cmos90|1204972178946|1243362147173||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981714344
+Cmlat2in5s;1{lay}||cmos90|1204972178946|1243362147173||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1244052682608
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NMetal-1-P-Active-Con|contact@0||15.5|-46.5||20.8|X|
 NMetal-1-N-Active-Con|contact@1||17.5|0||20.8|X|