add `reset` to Alu2

[fleet.git] / ships / Alu1.ship

diff --git a/ships/Alu1.ship b/ships/Alu1.ship
index 7f487c2..1ac349d 100644 (file)
--- a/ships/Alu1.ship
+++ b/ships/Alu1.ship
@@ -3,60 +3,74 @@ ship: Alu1
 == Ports ===========================================================
 data  in:   in
 data  in:   inOp
+  constant NEG: 0
+  constant INC: 1
+  constant DEC: 2
+  constant ABS: 3
 
 data  out:  out
 
-== Constants ========================================================
 == TeX ==============================================================
+
+{\tt Alu1} is a ``one-input'' arithmetic logic unit.  It includes
+logic for performing arithmetic operations on a single argument.
+Currently this includes
+negate ({\sc neg}),
+increment ({\sc inc}),
+decrement ({\sc dec}), and
+absolute value ({\sc abs}).
+
+\subsection*{Semantics}
+
+When a value is present at each of {\tt in} and {\tt inOp}, these two
+values are consumed.  Based on the value consumed at {\tt inOp}, the
+requested operation is performed on the value consumed from {\tt in}.
+The result of this operation is then made available at {\tt out}.
+
 == Fleeterpreter ====================================================
     public void service() {
-/*
-        if (in.dataReadyForShip() && op.dataReadyForShip()) {
-            int data   = in.removeDataForShip();
-            int opcode = in.removeDataForShip();
-            switch(opcode) {
-                case 0: out.addDataFromShip(-1 * data);      // NEG
+        if (box_in.dataReadyForShip() && box_inOp.dataReadyForShip() && box_out.readyForDataFromShip()) {
+            long data   = box_in.removeDataForShip();
+            long opcode = box_inOp.removeDataForShip();
+            switch((int)opcode) {
+                case 0: box_out.addDataFromShip(-1 * data);      // NEG
                     break;
-                case 1: out.addDataFromShip(data+1);         // INC
+                case 1: box_out.addDataFromShip(data+1);         // INC
                     break;
-                case 2: out.addDataFromShip(data-1);         // DEC
+                case 2: box_out.addDataFromShip(data-1);         // DEC
                     break;
-                case 3: out.addDataFromShip(Math.abs(data)); // ABS
+                case 3: box_out.addDataFromShip(Math.abs(data)); // ABS
                     break;
-                default: out.addDataFromShip(0);
+                default: box_out.addDataFromShip(0);
                     break;
             }
         }
-*/
     }
 
-== ArchSim ==============================================================
+== FleetSim ==============================================================
 == FPGA ==============================================================
-`include "macros.v"
-
-module alu1 (clk, 
-             a_r,    a_a_,  a_d,
-             op_r,   op_a_, op_d,
-             out_r_, out_a, out_d_);
-
-  input  clk;
-  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
-  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
-  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
-  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
-
-  reg                    have_a;
-  reg [(`DATAWIDTH-1):0] reg_a;
-  reg                    have_op;
-  reg [(`DATAWIDTH-1):0] reg_op;
+  reg                       have_a;
+  reg [(`PACKET_WIDTH-1):0] reg_a;
+  reg                       have_op;
+  reg [(`PACKET_WIDTH-1):0] reg_op;
+  reg [(`PACKET_WIDTH-1):0] extrabits;
 
   always @(posedge clk) begin
+    if (!rst) begin
+      have_a = 0;
+      have_op = 0;
+      `reset
+    end else begin
     if (!have_a) begin
-      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
+      `onread(in_r, in_a) have_a = 1; reg_a = in_d; end
       end
     if (!have_op) begin
-      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
+      `onread(inOp_r, inOp_a)
+         have_op   = 1;
+         reg_op    = inOp_d[(`DATAWIDTH-1):0];
+         extrabits = inOp_d[(`PACKET_WIDTH-1):`DATAWIDTH];
       end
+    end
   
     if (have_a && have_op) begin
       case (reg_op)
@@ -64,6 +78,8 @@ module alu1 (clk,
         1: out_d = reg_a+1;
         2: out_d = reg_a-1;
         3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
+        4: out_d = 37'b1111111111111111111111111111111111111;
+        5: out_d = extrabits;
         default: out_d = 0;
       endcase        
       `onwrite(out_r, out_a)
@@ -71,9 +87,38 @@ module alu1 (clk,
         have_op = 0;
       end
     end
+    end
   end
 
-endmodule
+== Test ==============================================================================
+// expected output
+
+#expect 10
+#expect 8
+#expect 9
+#expect -9
+#expect 9
+
+#ship debug        : Debug
+#ship alu1         : Alu1
+
+debug.in:   [*] take, deliver;
+alu1.in:
+  literal 9;
+  load repeat counter with 4; deliver;
+  take, deliver;
+
+alu1.out:
+  load repeat counter with 4; take, sendto debug.in;
+  sendto alu1.in;
+  take, sendto debug.in;
+
+alu1.inOp:
+   literal 1; deliver;
+   literal 2; deliver;
+   literal 3; deliver;
+   literal 0; deliver;
+   literal 0; deliver;
 
 
 == Contributors =========================================================