reg [(`PACKET_WIDTH-1):0] extrabits;
always @(posedge clk) begin
+ if (!rst) begin
+ have_a = 0;
+ have_op = 0;
+ `reset
+ end else begin
if (!have_a) begin
`onread(in_r, in_a) have_a = 1; reg_a = in_d; end
end
have_op = 0;
end
end
+ end
end
== Test ==============================================================================
// expected output
+
#expect 10
#expect 8
#expect 9
alu1.in:
literal 9;
load repeat counter with 4; deliver;
- [*] take, deliver;
+ take, deliver;
alu1.out:
load repeat counter with 4; take, sendto debug.in;
sendto alu1.in;
- [*] take, sendto debug.in;
+ take, sendto debug.in;
alu1.inOp:
literal 1; deliver;
literal 2; deliver;
literal 3; deliver;
- literal 0; load repeat counter with 2; deliver;
+ literal 0; deliver;
+ literal 0; deliver;
== Contributors =========================================================