FPGA-Fleet updates

[fleet.git] / ships / Alu1.ship

diff --git a/ships/Alu1.ship b/ships/Alu1.ship
index 9c15fd2..2a5019e 100644 (file)
--- a/ships/Alu1.ship
+++ b/ships/Alu1.ship
@@ -3,6 +3,9 @@ ship: Alu1
 == Ports ===========================================================
 data  in:   in
 data  in:   inOp
+data  in:   inOp.x
+data  in:   inOp.y
+data  in:   inOp.z
 
 data  out:  out
 
@@ -36,17 +39,22 @@ ABS:
 == FleetSim ==============================================================
 == FPGA ==============================================================
   reg                    have_a;
-  reg [(`DATAWIDTH-1):0] reg_a;
+  reg [(`PACKET_WIDTH-1):0] reg_a;
   reg                    have_op;
-  reg [(`DATAWIDTH-1):0] reg_op;
+  reg [(`PACKET_WIDTH-1):0] reg_op;
+  reg [(`PACKET_WIDTH-1):0] extrabits;
 
   always @(posedge clk) begin
     if (!have_a) begin
       `onread(in_r, in_a) have_a = 1; reg_a = in_d; end
       end
     if (!have_op) begin
-      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
+      `onread(inOp_r, inOp_a)
+         have_op   = 1;
+         reg_op    = inOp_d[(`DATAWIDTH-1):0];
+         extrabits = inOp_d[(`PACKET_WIDTH-1):`DATAWIDTH];
       end
+    end
   
     if (have_a && have_op) begin
       case (reg_op)
@@ -55,6 +63,7 @@ ABS:
         2: out_d = reg_a-1;
         3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
         4: out_d = 37'b1111111111111111111111111111111111111;
+        5: out_d = extrabits;
         default: out_d = 0;
       endcase        
       `onwrite(out_r, out_a)