some cleanups, build fpga stuff in build/fpga, not src

[fleet.git] / ships / Alu1.ship

diff --git a/ships/Alu1.ship b/ships/Alu1.ship
index 10170f7..4ef057a 100644 (file)
--- a/ships/Alu1.ship
+++ b/ships/Alu1.ship
@@ -3,35 +3,108 @@ ship: Alu1
 == Ports ===========================================================
 data  in:   in
 data  in:   inOp
+data  in:   inOp.x
+data  in:   inOp.y
+data  in:   inOp.z
 
 data  out:  out
 
 == Constants ========================================================
+NEG:
+INC:
+DEC:
+ABS:
+
 == TeX ==============================================================
 == Fleeterpreter ====================================================
     public void service() {
-/*
-        if (in.dataReadyForShip() && op.dataReadyForShip()) {
-            int data   = in.removeDataForShip();
-            int opcode = in.removeDataForShip();
-            switch(opcode) {
-                case 0: out.addDataFromShip(-1 * data);      // NEG
+        if (box_in.dataReadyForShip() && box_inOp.dataReadyForShip() && box_out.readyForDataFromShip()) {
+            long data   = box_in.removeDataForShip();
+            long opcode = box_inOp.removeDataForShip();
+            switch((int)opcode) {
+                case 0: box_out.addDataFromShip(-1 * data);      // NEG
                     break;
-                case 1: out.addDataFromShip(data+1);         // INC
+                case 1: box_out.addDataFromShip(data+1);         // INC
                     break;
-                case 2: out.addDataFromShip(data-1);         // DEC
+                case 2: box_out.addDataFromShip(data-1);         // DEC
                     break;
-                case 3: out.addDataFromShip(Math.abs(data)); // ABS
+                case 3: box_out.addDataFromShip(Math.abs(data)); // ABS
                     break;
-                default: out.addDataFromShip(0);
+                default: box_out.addDataFromShip(0);
                     break;
             }
         }
-*/
     }
 
-== ArchSim ==============================================================
+== FleetSim ==============================================================
 == FPGA ==============================================================
+  reg                       have_a;
+  reg [(`PACKET_WIDTH-1):0] reg_a;
+  reg                       have_op;
+  reg [(`PACKET_WIDTH-1):0] reg_op;
+  reg [(`PACKET_WIDTH-1):0] extrabits;
+
+  always @(posedge clk) begin
+    if (!have_a) begin
+      `onread(in_r, in_a) have_a = 1; reg_a = in_d; end
+      end
+    if (!have_op) begin
+      `onread(inOp_r, inOp_a)
+         have_op   = 1;
+         reg_op    = inOp_d[(`DATAWIDTH-1):0];
+         extrabits = inOp_d[(`PACKET_WIDTH-1):`DATAWIDTH];
+      end
+    end
+  
+    if (have_a && have_op) begin
+      case (reg_op)
+        0: out_d = -reg_a;
+        1: out_d = reg_a+1;
+        2: out_d = reg_a-1;
+        3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
+        4: out_d = 37'b1111111111111111111111111111111111111;
+        5: out_d = extrabits;
+        default: out_d = 0;
+      endcase        
+      `onwrite(out_r, out_a)
+        have_a  = 0;
+        have_op = 0;
+      end
+    end
+  end
+
+== Test ==============================================================================
+// expected output
+#expect 10
+#expect 8
+#expect 9
+#expect -9
+#expect 9
+
+#ship debug        : Debug
+#ship alu1         : Alu1
+
+debug.in:   [*] take, deliver;
+9:          sendto alu1.in;
+9:          sendto alu1.in;
+9:          sendto alu1.in;
+9:          sendto alu1.in;
+
+1:          sendto alu1.inOp;
+2:          sendto alu1.inOp;
+3:          sendto alu1.inOp;
+0:          sendto alu1.inOp;
+0:          sendto alu1.inOp;
+
+alu1.in:    [*] take, deliver;
+alu1.inOp:  [*] take, deliver;
+alu1.out:
+  [3] take, sendto debug.in;
+  take;
+  sendto debug.in;
+  sendto alu1.in;
+  [*] take, sendto debug.in;
+
 
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>