== Ports ===========================================================
data in: in
data in: inOp
+ constant NEG: 0
+ constant INC: 1
+ constant DEC: 2
+ constant ABS: 3
data out: out
-== Constants ========================================================
-ABS:
-NEG:
-INV:
-INC:
-DEC:
-
== TeX ==============================================================
+
+{\tt Alu1} is a ``one-input'' arithmetic logic unit. It includes
+logic for performing arithmetic operations on a single argument.
+Currently this includes
+negate ({\sc neg}),
+increment ({\sc inc}),
+decrement ({\sc dec}), and
+absolute value ({\sc abs}).
+
+\subsection*{Semantics}
+
+When a value is present at each of {\tt in} and {\tt inOp}, these two
+values are consumed. Based on the value consumed at {\tt inOp}, the
+requested operation is performed on the value consumed from {\tt in}.
+The result of this operation is then made available at {\tt out}.
+
== Fleeterpreter ====================================================
public void service() {
- if (box_in.dataReadyForShip() && box_inOp.dataReadyForShip()) {
- int data = box_in.removeDataForShip();
- int opcode = box_inOp.removeDataForShip();
- switch(opcode) {
+ if (box_in.dataReadyForShip() && box_inOp.dataReadyForShip() && box_out.readyForDataFromShip()) {
+ long data = box_in.removeDataForShip();
+ long opcode = box_inOp.removeDataForShip();
+ switch((int)opcode) {
case 0: box_out.addDataFromShip(-1 * data); // NEG
break;
case 1: box_out.addDataFromShip(data+1); // INC
== FleetSim ==============================================================
== FPGA ==============================================================
- reg have_a;
- reg [(`DATAWIDTH-1):0] reg_a;
- reg have_op;
- reg [(`DATAWIDTH-1):0] reg_op;
always @(posedge clk) begin
- if (!have_a) begin
- `onread(in_r, in_a) have_a = 1; reg_a = in_d; end
- end
- if (!have_op) begin
- `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
- end
-
- if (have_a && have_op) begin
- case (reg_op)
- 0: out_d = -reg_a;
- 1: out_d = reg_a+1;
- 2: out_d = reg_a-1;
- 3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
- 4: out_d = 37'b1111111111111111111111111111111111111;
- default: out_d = 0;
- endcase
- `onwrite(out_r, out_a)
- have_a = 0;
- have_op = 0;
+ if (!rst) begin
+ `reset
+ end else begin
+ if (out_r && out_a) out_r <= 0;
+ if (!in_r && in_a) in_a <= 0;
+ if (!inOp_r && inOp_a) inOp_a <= 0;
+ if (!out_r && !out_a && in_r && !in_a && inOp_r && !inOp_a) begin
+ out_r <= 1;
+ in_a <= 1;
+ inOp_a <= 1;
+ case (inOp_d)
+ 0: out_d <= -in_d;
+ 1: out_d <= in_d+1;
+ 2: out_d <= in_d-1;
+ 3: out_d <= (in_d<0) ? (-in_d) : in_d;
+ default: out_d <= 0;
+ endcase
end
end
end
+== Test ==============================================================================
+// expected output
+
+#expect 10
+#expect 8
+#expect 9
+#expect -9
+#expect 9
+
+#ship debug : Debug
+#ship alu1 : Alu1
+#ship fifo : Fifo
+
+debug.in:
+ [*] take, deliver;
+
+alu1.in:
+ literal 9;
+ load repeat counter with 4;
+ deliver;
+ take, deliver;
+
+alu1.out:
+ load repeat counter with 4;
+ take, sendto debug.in;
+ sendto alu1.in;
+ take, sendto debug.in;
+
+alu1.inOp:
+ notify fifo.out;
+ [*] take, deliver, notify fifo.out;
+
+fifo.out:
+ [*] wait, take, sendto alu1.inOp;
+
+fifo.in:
+ literal 1; deliver;
+ literal 2; deliver;
+ literal 3; deliver;
+ literal 0; deliver;
+ literal 0; deliver;
+
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>