autogenerate parts of Alu1, Alu2, Lut3 verilog

[fleet.git] / ships / Alu1.ship

diff --git a/ships/Alu1.ship b/ships/Alu1.ship
index 7ee1de9..abaee8a 100644 (file)
--- a/ships/Alu1.ship
+++ b/ships/Alu1.ship
@@ -16,41 +16,26 @@ DEC:
 == TeX ==============================================================
 == Fleeterpreter ====================================================
     public void service() {
-/*
-        if (in.dataReadyForShip() && op.dataReadyForShip()) {
-            int data   = in.removeDataForShip();
-            int opcode = in.removeDataForShip();
+        if (box_in.dataReadyForShip() && box_inOp.dataReadyForShip()) {
+            int data   = box_in.removeDataForShip();
+            int opcode = box_inOp.removeDataForShip();
             switch(opcode) {
-                case 0: out.addDataFromShip(-1 * data);      // NEG
+                case 0: box_out.addDataFromShip(-1 * data);      // NEG
                     break;
-                case 1: out.addDataFromShip(data+1);         // INC
+                case 1: box_out.addDataFromShip(data+1);         // INC
                     break;
-                case 2: out.addDataFromShip(data-1);         // DEC
+                case 2: box_out.addDataFromShip(data-1);         // DEC
                     break;
-                case 3: out.addDataFromShip(Math.abs(data)); // ABS
+                case 3: box_out.addDataFromShip(Math.abs(data)); // ABS
                     break;
-                default: out.addDataFromShip(0);
+                default: box_out.addDataFromShip(0);
                     break;
             }
         }
-*/
     }
 
 == FleetSim ==============================================================
 == FPGA ==============================================================
-`include "macros.v"
-
-module alu1 (clk, 
-             a_r,    a_a_,  a_d,
-             op_r,   op_a_, op_d,
-             out_r_, out_a, out_d_);
-
-  input  clk;
-  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
-  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
-  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
-  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
-
   reg                    have_a;
   reg [(`DATAWIDTH-1):0] reg_a;
   reg                    have_op;
@@ -58,10 +43,10 @@ module alu1 (clk,
 
   always @(posedge clk) begin
     if (!have_a) begin
-      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
+      `onread(in_r, in_a) have_a = 1; reg_a = in_d; end
       end
     if (!have_op) begin
-      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
+      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
       end
   
     if (have_a && have_op) begin
@@ -70,6 +55,7 @@ module alu1 (clk,
         1: out_d = reg_a+1;
         2: out_d = reg_a-1;
         3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
+        4: out_d = 37'b1111111111111111111111111111111111111;
         default: out_d = 0;
       endcase        
       `onwrite(out_r, out_a)
@@ -79,8 +65,6 @@ module alu1 (clk,
     end
   end
 
-endmodule
-
 
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>