clean up constants in Alu1

[fleet.git] / ships / Alu1.ship

diff --git a/ships/Alu1.ship b/ships/Alu1.ship
index 10170f7..baa5662 100644 (file)
--- a/ships/Alu1.ship
+++ b/ships/Alu1.ship
@@ -7,31 +7,63 @@ data  in:   inOp
 data  out:  out
 
 == Constants ========================================================
+NEG:
+INC:
+DEC:
+ABS:
+
 == TeX ==============================================================
 == Fleeterpreter ====================================================
     public void service() {
-/*
-        if (in.dataReadyForShip() && op.dataReadyForShip()) {
-            int data   = in.removeDataForShip();
-            int opcode = in.removeDataForShip();
+        if (box_in.dataReadyForShip() && box_inOp.dataReadyForShip()) {
+            int data   = box_in.removeDataForShip();
+            int opcode = box_inOp.removeDataForShip();
             switch(opcode) {
-                case 0: out.addDataFromShip(-1 * data);      // NEG
+                case 0: box_out.addDataFromShip(-1 * data);      // NEG
                     break;
-                case 1: out.addDataFromShip(data+1);         // INC
+                case 1: box_out.addDataFromShip(data+1);         // INC
                     break;
-                case 2: out.addDataFromShip(data-1);         // DEC
+                case 2: box_out.addDataFromShip(data-1);         // DEC
                     break;
-                case 3: out.addDataFromShip(Math.abs(data)); // ABS
+                case 3: box_out.addDataFromShip(Math.abs(data)); // ABS
                     break;
-                default: out.addDataFromShip(0);
+                default: box_out.addDataFromShip(0);
                     break;
             }
         }
-*/
     }
 
-== ArchSim ==============================================================
+== FleetSim ==============================================================
 == FPGA ==============================================================
+  reg                    have_a;
+  reg [(`DATAWIDTH-1):0] reg_a;
+  reg                    have_op;
+  reg [(`DATAWIDTH-1):0] reg_op;
+
+  always @(posedge clk) begin
+    if (!have_a) begin
+      `onread(in_r, in_a) have_a = 1; reg_a = in_d; end
+      end
+    if (!have_op) begin
+      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
+      end
+  
+    if (have_a && have_op) begin
+      case (reg_op)
+        0: out_d = -reg_a;
+        1: out_d = reg_a+1;
+        2: out_d = reg_a-1;
+        3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
+        4: out_d = 37'b1111111111111111111111111111111111111;
+        default: out_d = 0;
+      endcase        
+      `onwrite(out_r, out_a)
+        have_a  = 0;
+        have_op = 0;
+      end
+    end
+  end
+
 
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>