disable Alu3 test temporarily (clogs switch fabric with two-instruction literals)

[fleet.git] / ships / Alu2.ship

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index 1314407..30ed60c 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -1,40 +1,68 @@
 ship: Alu2
 
 == Ports ===========================================================
-data  in:   a
-data  in:   b
-data  in:   op
+data  in:   in1
+data  in:   in2
+data  in:   inOp
+  constant ADD: 0
+  constant SUB: 1
+  constant MAX: 2
+  constant MIN: 3
 
 data  out:  out
 
-== Constants ========================================================
-ADD: add the two arguments; treat link as carry
-SUB: subtract the two arguments; treat link as carry
 
 == TeX ==============================================================
-This ship is a two-input arithmetic unit.  It features several
-opcodes, such as {\tt ADD} and {\tt SUB}.  In my opinion, it is
-niftycool.
+
+{\tt Alu2} is a ``two-input'' arithmetic logic unit.  It includes
+logic for performing arithmetic operations on a pair of arguments.
+Currently this includes
+addition ({\sc add}),
+subtraction ({\sc sub}),
+maximum ({\sc max}), and
+minimum ({\sc min}).
+
+\subsection*{Semantics}
+
+When a value is present at each of {\tt in1}, {\tt in2} and {\tt
+inOp}, these three values are consumed.  Based on the value consumed
+at {\tt inOp}, the requested operation is performed on the values
+consumed from {\tt in1} and {\tt in2}.  The result of this operation
+is then made available at {\tt out}.
+
+\subsection*{To Do}
+
+The {\it link bit} and other features of \cite{ies31} are not yet
+implemented.
+
+The carry-in, carry-out, zero-test, negative-test, and overflow-test
+flags typically present in a conventional processor ALU are also not
+yet implemented.
 
 == Fleeterpreter ====================================================
+public long resolveLiteral(String literal) {
+  if (literal.equals("ADD")) return 0;
+  if (literal.equals("SUB")) return 1;
+  if (literal.equals("MAX")) return 2;
+  if (literal.equals("MIN")) return 3;
+  return super.resolveLiteral(literal);
+}
 public void service() {
-  if (box_a.dataReadyForShip() &&
-      box_b.dataReadyForShip() &&
-      box_op.dataReadyForShip() &&
-      box_out.readyForItemFromShip()) {
-      int a      = box_a.removeDataForShip();
-      int b      = box_b.removeDataForShip();
-      int op     = box_op.removeDataForShip();
-      switch(op) {
+  if (box_in1.dataReadyForShip() &&
+      box_in2.dataReadyForShip() &&
+      box_inOp.dataReadyForShip() &&
+      box_out.readyForDataFromShip()) {
+      long a      = box_in1.removeDataForShip();
+      long b      = box_in2.removeDataForShip();
+      long op     = box_inOp.removeDataForShip();
+      switch((int)op) {
           case 0: box_out.addDataFromShip(a+b); // ADD
               break;
           case 1: box_out.addDataFromShip(a-b); // SUB
               break;
-          case 2: box_out.addDataFromShip(a*b); // MUL
+          case 2: box_out.addDataFromShip(Math.max(a,b)); // MAX
               break;
-          case 3: box_out.addDataFromShip(a/b); // DIV
-              break;
-          case 4: box_out.addDataFromShip(a%b); // REM
+          case 3: box_out.addDataFromShip(Math.min(a,b)); // MIN
               break;
           default: box_out.addDataFromShip(0);
               break;
@@ -42,9 +70,72 @@ public void service() {
   }
 }
 
-== ArchSim ==============================================================
+== FleetSim ==============================================================
 
 == FPGA ==============================================================
 
+  reg                    have_a;
+  reg [(`DATAWIDTH-1):0] reg_a;
+  reg                    have_b;
+  reg [(`DATAWIDTH-1):0] reg_b;
+  reg                    have_op;
+  reg [(`DATAWIDTH-1):0] reg_op;
+
+  always @(posedge clk) begin
+    if (!have_a) begin
+      `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
+      end
+    if (!have_b) begin
+      `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
+      end
+    if (!have_op) begin
+      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
+      end
+  
+    if (have_a && have_b && have_op) begin
+      case (reg_op)
+        0: out_d = reg_a + reg_b;
+        1: out_d = reg_a - reg_b;
+        2: out_d = reg_a > reg_b ? reg_a : reg_b;
+        3: out_d = reg_a > reg_b ? reg_b : reg_a;
+        default: out_d = 0;
+      endcase        
+      `onwrite(out_r, out_a)
+        have_a  = 0;
+        have_b  = 0;
+        have_op = 0;
+      end
+    end
+  end
+
+== Test ==============================================================================
+// expected output
+#ship debug : Debug
+#ship alu   : Alu2
+
+#expect 17
+#expect 1
+#expect 8
+#expect 9
+
+debug.in:   [*] take, deliver;
+alu.in1:
+  literal 9; [4] deliver;
+
+alu.in2:
+  literal 8; [4] deliver;
+
+alu.in1:    [*] take, deliver;
+alu.in2:    [*] take, deliver;
+alu.out:    [*] take, sendto debug.in;
+
+alu.inOp:
+ literal Alu2.inOp[ADD]; deliver;
+ literal Alu2.inOp[SUB]; deliver;
+ literal Alu2.inOp[MIN]; deliver;
+ literal Alu2.inOp[MAX]; deliver;
+
+
+
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>