reorder Alu3 instructions to deal with two-instruction literals

[fleet.git] / ships / Alu2.ship

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index 400eb08..30ed60c 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -13,22 +13,31 @@ data  out:  out
 
 
 == TeX ==============================================================
-This ship is a two-input arithmetic unit.  It features several
-opcodes, such as {\tt ADD} and {\tt SUB}.  In my opinion, it is
-niftycool.
 
-FIXME: implement all the link bit stuff
+{\tt Alu2} is a ``two-input'' arithmetic logic unit.  It includes
+logic for performing arithmetic operations on a pair of arguments.
+Currently this includes
+addition ({\sc add}),
+subtraction ({\sc sub}),
+maximum ({\sc max}), and
+minimum ({\sc min}).
 
-Use carry-in bit to create a selector?  Perhaps a waste of an ALU.
+\subsection*{Semantics}
 
-Flags: zero, negative, overflow, ?
+When a value is present at each of {\tt in1}, {\tt in2} and {\tt
+inOp}, these three values are consumed.  Based on the value consumed
+at {\tt inOp}, the requested operation is performed on the values
+consumed from {\tt in1} and {\tt in2}.  The result of this operation
+is then made available at {\tt out}.
 
-\begin{verbatim}
-move elsewhere:
-//MUL:
-//DIV:
-//MOD:
-\end{verbatim}
+\subsection*{To Do}
+
+The {\it link bit} and other features of \cite{ies31} are not yet
+implemented.
+
+The carry-in, carry-out, zero-test, negative-test, and overflow-test
+flags typically present in a conventional processor ALU are also not
+yet implemented.
 
 == Fleeterpreter ====================================================
 public long resolveLiteral(String literal) {