update more test cases to use literal-at-pump

[fleet.git] / ships / Alu2.ship

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index 1c567c9..400eb08 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -4,37 +4,56 @@ ship: Alu2
 data  in:   in1
 data  in:   in2
 data  in:   inOp
+  constant ADD: 0
+  constant SUB: 1
+  constant MAX: 2
+  constant MIN: 3
 
 data  out:  out
 
-== Constants ========================================================
-ADD: add the two arguments; treat link as carry
-SUB: subtract the two arguments; treat link as carry
 
 == TeX ==============================================================
 This ship is a two-input arithmetic unit.  It features several
 opcodes, such as {\tt ADD} and {\tt SUB}.  In my opinion, it is
 niftycool.
 
+FIXME: implement all the link bit stuff
+
+Use carry-in bit to create a selector?  Perhaps a waste of an ALU.
+
+Flags: zero, negative, overflow, ?
+
+\begin{verbatim}
+move elsewhere:
+//MUL:
+//DIV:
+//MOD:
+\end{verbatim}
+
 == Fleeterpreter ====================================================
+public long resolveLiteral(String literal) {
+  if (literal.equals("ADD")) return 0;
+  if (literal.equals("SUB")) return 1;
+  if (literal.equals("MAX")) return 2;
+  if (literal.equals("MIN")) return 3;
+  return super.resolveLiteral(literal);
+}
 public void service() {
   if (box_in1.dataReadyForShip() &&
       box_in2.dataReadyForShip() &&
       box_inOp.dataReadyForShip() &&
-      box_out.readyForItemFromShip()) {
-      int a      = box_in1.removeDataForShip();
-      int b      = box_in2.removeDataForShip();
-      int op     = box_inOp.removeDataForShip();
-      switch(op) {
+      box_out.readyForDataFromShip()) {
+      long a      = box_in1.removeDataForShip();
+      long b      = box_in2.removeDataForShip();
+      long op     = box_inOp.removeDataForShip();
+      switch((int)op) {
           case 0: box_out.addDataFromShip(a+b); // ADD
               break;
           case 1: box_out.addDataFromShip(a-b); // SUB
               break;
-          case 2: box_out.addDataFromShip(a*b); // MUL
-              break;
-          case 3: box_out.addDataFromShip(a/b); // DIV
+          case 2: box_out.addDataFromShip(Math.max(a,b)); // MAX
               break;
-          case 4: box_out.addDataFromShip(a%b); // REM
+          case 3: box_out.addDataFromShip(Math.min(a,b)); // MIN
               break;
           default: box_out.addDataFromShip(0);
               break;
@@ -42,23 +61,9 @@ public void service() {
   }
 }
 
-== ArchSim ==============================================================
+== FleetSim ==============================================================
 
 == FPGA ==============================================================
-`include "macros.v"
-
-module alu2 (clk, 
-             a_r,    a_a_,  a_d,
-             b_r,    b_a_,  b_d,
-             op_r,   op_a_, op_d,
-             out_r_, out_a, out_d_);
-
-  input  clk;
-  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
-  `input(b_r,    b_a,    b_a_,  [(`DATAWIDTH-1):0], b_d)
-  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
-  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
-  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
 
   reg                    have_a;
   reg [(`DATAWIDTH-1):0] reg_a;
@@ -69,22 +74,21 @@ module alu2 (clk,
 
   always @(posedge clk) begin
     if (!have_a) begin
-      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
+      `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
       end
     if (!have_b) begin
-      `onread(b_r, b_a) have_b = 1; reg_b = b_d; end
+      `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
       end
     if (!have_op) begin
-      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
+      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
       end
   
     if (have_a && have_b && have_op) begin
       case (reg_op)
         0: out_d = reg_a + reg_b;
         1: out_d = reg_a - reg_b;
-        //2: out_d = reg_a * reg_b; // will not synthesize --AM
-        //3: out_d = reg_a / reg_b; // will not synthesize --AM
-        //4: out_d = reg_a % reg_b; // will not synthesize --AM
+        2: out_d = reg_a > reg_b ? reg_a : reg_b;
+        3: out_d = reg_a > reg_b ? reg_b : reg_a;
         default: out_d = 0;
       endcase        
       `onwrite(out_r, out_a)
@@ -95,7 +99,32 @@ module alu2 (clk,
     end
   end
 
-endmodule
+== Test ==============================================================================
+// expected output
+#ship debug : Debug
+#ship alu   : Alu2
+
+#expect 17
+#expect 1
+#expect 8
+#expect 9
+
+debug.in:   [*] take, deliver;
+alu.in1:
+  literal 9; [4] deliver;
+
+alu.in2:
+  literal 8; [4] deliver;
+
+alu.in1:    [*] take, deliver;
+alu.in2:    [*] take, deliver;
+alu.out:    [*] take, sendto debug.in;
+
+alu.inOp:
+ literal Alu2.inOp[ADD]; deliver;
+ literal Alu2.inOp[SUB]; deliver;
+ literal Alu2.inOp[MIN]; deliver;
+ literal Alu2.inOp[MAX]; deliver;