factor out verilog headers on Alu2 ship

[fleet.git] / ships / Alu2.ship

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index 1c567c9..ab4044e 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -10,12 +10,27 @@ data  out:  out
 == Constants ========================================================
 ADD: add the two arguments; treat link as carry
 SUB: subtract the two arguments; treat link as carry
+MUL:
+DIV:
+MOD:
+REM:
+MAX:
+MIN:
+SORT: output min(in1,in2) followed by max(in1,in2) (FIXME: redundant?)
 
 == TeX ==============================================================
 This ship is a two-input arithmetic unit.  It features several
 opcodes, such as {\tt ADD} and {\tt SUB}.  In my opinion, it is
 niftycool.
 
+FIXME: implement all the link bit stuff
+
+Use carry-in bit to create a selector?  Perhaps a waste of an ALU.
+
+Carry-save / carry completion stuff.
+
+Flags: zero, negative, overflow, ?
+
 == Fleeterpreter ====================================================
 public void service() {
   if (box_in1.dataReadyForShip() &&
@@ -42,22 +57,16 @@ public void service() {
   }
 }
 
-== ArchSim ==============================================================
+== FleetSim ==============================================================
 
 == FPGA ==============================================================
-`include "macros.v"
-
-module alu2 (clk, 
-             a_r,    a_a_,  a_d,
-             b_r,    b_a_,  b_d,
-             op_r,   op_a_, op_d,
-             out_r_, out_a, out_d_);
 
   input  clk;
-  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
-  `input(b_r,    b_a,    b_a_,  [(`DATAWIDTH-1):0], b_d)
-  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
+  `input(in1_r,    in1_a,    in1_a_,  [(`DATAWIDTH-1):0], in1_d)
+  `input(in2_r,    in2_a,    in2_a_,  [(`DATAWIDTH-1):0], in2_d)
+  `input(inOp_r,   inOp_a,   inOp_a_, [(`DATAWIDTH-1):0], inOp_d)
   `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
+
   `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
 
   reg                    have_a;
@@ -69,13 +78,13 @@ module alu2 (clk,
 
   always @(posedge clk) begin
     if (!have_a) begin
-      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
+      `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
       end
     if (!have_b) begin
-      `onread(b_r, b_a) have_b = 1; reg_b = b_d; end
+      `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
       end
     if (!have_op) begin
-      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
+      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
       end
   
     if (have_a && have_b && have_op) begin