data in: in1
data in: in2
data in: inOp
+ constant ADD: 0
+ constant SUB: 1
+ constant MAX: 2
+ constant MIN: 3
data out: out
-== Constants ========================================================
-ADD: add the two arguments; treat link as carry
-SUB: subtract the two arguments; treat link as carry
-MAX:
-MIN:
== TeX ==============================================================
-This ship is a two-input arithmetic unit. It features several
-opcodes, such as {\tt ADD} and {\tt SUB}. In my opinion, it is
-niftycool.
-FIXME: implement all the link bit stuff
+{\tt Alu2} is a ``two-input'' arithmetic logic unit. It includes
+logic for performing arithmetic operations on a pair of arguments.
+Currently this includes
+addition ({\sc add}),
+subtraction ({\sc sub}),
+maximum ({\sc max}), and
+minimum ({\sc min}).
-Use carry-in bit to create a selector? Perhaps a waste of an ALU.
+\subsection*{Semantics}
-Flags: zero, negative, overflow, ?
+When a value is present at each of {\tt in1}, {\tt in2} and {\tt
+inOp}, these three values are consumed. Based on the value consumed
+at {\tt inOp}, the requested operation is performed on the values
+consumed from {\tt in1} and {\tt in2}. The result of this operation
+is then made available at {\tt out}.
-\begin{verbatim}
-move elsewhere:
-//MUL:
-//DIV:
-//MOD:
-\end{verbatim}
+\subsection*{To Do}
+
+The {\it link bit} and other features of \cite{ies31} are not yet
+implemented.
+
+The carry-in, carry-out, zero-test, negative-test, and overflow-test
+flags typically present in a conventional processor ALU are also not
+yet implemented.
== Fleeterpreter ====================================================
public long resolveLiteral(String literal) {
end
== Test ==============================================================================
-#skip
-
+// expected output
+#ship debug : Debug
+#ship alu : Alu2
+
+#expect 17
+#expect 1
+#expect 8
+#expect 9
+
+debug.in: [*] take, deliver;
+alu.in1:
+ literal 9; load repeat counter with 4; deliver;
+
+alu.in2:
+ literal 8; load repeat counter with 4; deliver;
+
+alu.in1: [*] take, deliver;
+alu.in2: [*] take, deliver;
+alu.out: [*] take, sendto debug.in;
+
+alu.inOp:
+ literal Alu2.inOp[ADD]; deliver;
+ literal Alu2.inOp[SUB]; deliver;
+ literal Alu2.inOp[MIN]; deliver;
+ literal Alu2.inOp[MAX]; deliver;