autogenerate parts of Alu1, Alu2, Lut3 verilog

[fleet.git] / ships / Alu2.ship

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index 392be46..ea5ffcb 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -57,14 +57,6 @@ public void service() {
 
 == FPGA ==============================================================
 
-  input  clk;
-  `input(in1_r,    in1_a,    in1_a_,  [(`DATAWIDTH-1):0], in1_d)
-  `input(in2_r,    in2_a,    in2_a_,  [(`DATAWIDTH-1):0], in2_d)
-  `input(inOp_r,   inOp_a,   inOp_a_, [(`DATAWIDTH-1):0], inOp_d)
-  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
-
-  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
-
   reg                    have_a;
   reg [(`DATAWIDTH-1):0] reg_a;
   reg                    have_b;
@@ -87,9 +79,6 @@ public void service() {
       case (reg_op)
         0: out_d = reg_a + reg_b;
         1: out_d = reg_a - reg_b;
-        //2: out_d = reg_a * reg_b; // will not synthesize --AM
-        //3: out_d = reg_a / reg_b; // will not synthesize --AM
-        //4: out_d = reg_a % reg_b; // will not synthesize --AM
         default: out_d = 0;
       endcase        
       `onwrite(out_r, out_a)
@@ -100,7 +89,6 @@ public void service() {
     end
   end
 
-endmodule