reg wrote; initial wrote = 0;
always @(posedge clk) begin
+ if (!rst) begin
+ `reset
+ mode = 0;
+ have_in1 <= 0;
+ have_in2 <= 0;
+ have_in3 <= 0;
+ keep_in1 <= 0;
+ keep_in2 <= 0;
+ keep_in3 <= 0;
+ have_out1 <= 0;
+ have_out2 <= 0;
+ bitstorage = 0;
+ bitstorage_count <= 0;
+ wrote = 0;
+ end else begin
wrote = 0;
if (bitstorage_count >= `DATAWIDTH) begin
outBits_d = bitstorage[(`DATAWIDTH-1):0];
have_in2 <= 0;
have_in3 <= 0;
end
+ end
end
== Test ========================================================================
-
#ship alu3 : Alu3
#ship lut3 : Lut3
#ship bitfifo : BitFifo