shortcut to: in1
data out: out2
shortcut to: in2
-data out: out3
- shortcut to: in3
data out: outBits
== Constants ========================================================
== TeX ==============================================================
+{\tt Alu3} is a three-input adder which produces a pair of outputs in
+carry-save form. It has no opcode input.
+
+This ship also contains a private ``bit fifo'' similar to the {\tt
+BitFifo} ship, except that only the dequeueing (output) interface is
+exposed to the programmer. Each addition operation performed causes
+the lowest bit of the {\it save} output to be enqueued into the bit
+fifo. This can be used to produce a very efficient multiplier; see
+the test case for this ship for more details.
+
+\subsection*{Semantics}
+
+When a value is present at each of {\tt in1}, {\tt in2} and {\tt in3},
+these three values are consumed. The {\it carry} result of carry-save
+addition is placed in {\tt out1}, and the {\it save} result of
+carry-save addition is placed in {\tt out2}.
+
+\subsection*{To Do}
+
+Is the second output supposed to be shifted?
+
+Provide a way to clear/flush the internal bitfifo.
+
+Do we even need this? Can we do the same thing with {\tt Lut3} and
+{\tt BitFifo} together?
+
+
== Fleeterpreter ====================================================
-int count = 74;
-Bitfifo.BitStorage outBits = new Bitfifo.BitStorage(74);
+boolean mode = false;
+BitFifo.BitStorage outBits = new BitFifo.BitStorage(74);
public void service() {
+ if (outBits.size() >= 37) {
+ if (box_outBits.readyForDataFromShip()) {
+ box_outBits.addDataFromShip(outBits.get(37));
+ }
+ } else
if (box_in1.dataReadyForShip() &&
box_in2.dataReadyForShip() &&
box_in3.dataReadyForShip() &&
outBits.hasSpace(1) &&
box_out1.readyForDataFromShip() &&
- box_out2.readyForDataFromShip() &&
- box_out3.readyForDataFromShip()) {
+ box_out2.readyForDataFromShip()) {
long v1 = box_in1.removeDataForShip();
long v2 = box_in2.removeDataForShip();
long v3 = box_in3.removeDataForShip();
long o1, o2, o3;
- if (count % 2 == 0) {
- o1 = v1;
- o2 = v2 >>> 1;
- o3 = ((v2 & 0x1L) == 0) ? 0 : v1;
- } else {
- o1 = ((v1 & v2) | (v2 & v3) | (v1 & v3))/* << 1*/;
- o2 = (v1 ^ v2 ^ v3) >> 1;
- o3 = 0;
- outBits.add((v1 ^ v2 ^ v3) & 0x1L, 1);
- }
+ o1 = ((v1 & v2) | (v2 & v3) | (v1 & v3))/* << 1*/;
+ o2 = (v1 ^ v2 ^ v3) >> 1;
+ outBits.add((v1 ^ v2 ^ v3) & 0x1L, 1);
box_out1.addDataFromShip(o1);
box_out2.addDataFromShip(o2);
- box_out3.addDataFromShip(o3);
- count--;
- // This should be removed
- if (count == 0) {
- for (int i = 0; i < 37; i++) {
- v1 = o1;
- v2 = o2;
- v3 = o3;
- o1 = ((v1 & v2) | (v2 & v3) | (v1 & v3))/* << 1*/;
- o2 = (v1 ^ v2 ^ v3) >> 1;
- o3 = 0;
- outBits.add((v1 ^ v2 ^ v3) & 0x1L, 1);
- }
- count = 74;
- }
- }
- if (box_outBits.readyForDataFromShip() &&
- outBits.size() >= 37) {
- box_outBits.addDataFromShip(outBits.get(37));
}
}
== FPGA ==============================================================
- reg have_a;
- reg [(`DATAWIDTH-1):0] a;
- reg have_b;
- reg [(`DATAWIDTH-1):0] b;
- reg have_c;
- reg [(`DATAWIDTH-1):0] c;
- reg have_out1;
- reg have_out2;
+ reg mode; initial mode = 0;
+ reg have_in1; initial have_in1 = 0;
+ reg have_in2; initial have_in2 = 0;
+ reg have_in3; initial have_in3 = 0;
+ reg [(`DATAWIDTH-1):0] keep_in1; initial keep_in1 = 0;
+ reg [(`DATAWIDTH-1):0] keep_in2; initial keep_in2 = 0;
+ reg [(`DATAWIDTH-1):0] keep_in3; initial keep_in3 = 0;
+ reg have_out1; initial have_out1 = 0;
+ reg have_out2; initial have_out2 = 0;
+ reg [73:0] bitstorage; initial bitstorage = 0;
+ reg [7:0] bitstorage_count; initial bitstorage_count = 0;
+ reg wrote; initial wrote = 0;
always @(posedge clk) begin
- if (have_out1) begin
+ if (!rst) begin
+ `reset
+ mode = 0;
+ have_in1 <= 0;
+ have_in2 <= 0;
+ have_in3 <= 0;
+ keep_in1 <= 0;
+ keep_in2 <= 0;
+ keep_in3 <= 0;
+ have_out1 <= 0;
+ have_out2 <= 0;
+ bitstorage = 0;
+ bitstorage_count <= 0;
+ wrote = 0;
+ end else begin
+ wrote = 0;
+ if (bitstorage_count >= `DATAWIDTH) begin
+ outBits_d = bitstorage[(`DATAWIDTH-1):0];
+ `onwrite(outBits_r, outBits_a)
+ bitstorage_count <= 0;
+ bitstorage = bitstorage >> `DATAWIDTH;
+ end
+ end else if (have_out1) begin
`onwrite(out1_r, out1_a) have_out1 <= 0; end
-
end else if (have_out2) begin
`onwrite(out2_r, out2_a) have_out2 <= 0; end
-
- end else if (!have_out1 && !have_out2) begin
- if (!have_a) begin
- `onread(in1_r, in1_a) have_a <= 1; a <= in1_d; end
- end
- if (!have_b) begin
- `onread(in2_r, in2_a) have_b <= 1; b <= in2_d; end
- end
- if (!have_c) begin
- `onread(in3_r, in3_a) have_c <= 1; c <= in3_d; end
- end
-
- if (have_a && have_b && have_c) begin
- out1_d <= { { ((a & b) | (b & c) | (a & c)) } , 1'b0 };
- out2_d <= a ^ b ^ c;
- have_a <= 0;
- have_b <= 0;
- have_c <= 0;
+ end else if (!have_in1) begin
+ `onread(in1_r, in1_a) have_in1 <= 1; keep_in1 <= in1_d; end
+ end else if (!have_in2) begin
+ `onread(in2_r, in2_a) have_in2 <= 1; keep_in2 <= in2_d; end
+ end else if (!have_in3) begin
+ `onread(in3_r, in3_a) have_in3 <= 1; keep_in3 <= in3_d; end
+ end else begin
+ out1_d <= { ((keep_in1 & keep_in2) | (keep_in2 & keep_in3) | (keep_in1 & keep_in3)) };
+ out2_d <= { 1'b0, (keep_in1[(`DATAWIDTH-1):1] ^
+ keep_in2[(`DATAWIDTH-1):1] ^
+ keep_in3[(`DATAWIDTH-1):1]) };
+ bitstorage[bitstorage_count] = (keep_in1[0] ^ keep_in2[0] ^ keep_in3[0]);
+ bitstorage_count <= bitstorage_count+1;
have_out1 <= 1;
have_out2 <= 1;
- end
+ have_in1 <= 0;
+ have_in2 <= 0;
+ have_in3 <= 0;
end
+ end
+
end
+
== Test ========================================================================
-#expect 100488372224
-#expect 8
-
-
-#ship alu3 : Alu3
-#ship debug : Debug
-
-1000000: sendto alu3.in1;
-1200000: sendto alu3.in2;
-0: sendto alu3.in3;
-0: sendto alu3.in1;
-0: sendto alu3.in2;
-alu3.in1: [*] take, deliver;
-alu3.in2: [*] take, deliver;
-alu3.in3: [*] take, deliver;
-alu3.out1: [74] take, sendto alu3.in1;
-alu3.out2: [74] take, sendto alu3.in2;
-alu3.out3: [74] take, sendto alu3.in3;
-alu3.outBits: [2] take, sendto debug.in;
+#ship alu3 : Alu3
+#ship lut3 : Lut3
+#ship bitfifo : BitFifo
+#ship debug : Debug
+#ship fifo : Fifo
+
+#expect -66848683
+#expect 18682
+
+// 0: 100100100111110000000
+// sel 011110100001001000000
+// 1: 111000101000011000011
+// r: 111000100110111000000
+
+bitfifo.in:
+ literal 10000;
+ deliver; // deliver a junk word
+ load repeat counter with 37; deliver; // deliver it 37 times (once per bit)
+ literal 0;
+ load repeat counter with 38; deliver; // deliver it 37 times
+
+// insert bits in lsb order
+bitfifo.inOp:
+ literal BitFifo.inOp[lsbFirst,take=37];
+ [*] deliver;
+
+// toss out 37 bits, take one, repeat. sign extend the result
+bitfifo.outOp:
+ literal BitFifo.outOp[drop=37,take=1,signExtend];
+ [*] deliver;
+
+bitfifo.out: [*] wait, take, sendto lut3.in2;
+lut3.in2: load repeat counter with 4; notify bitfifo.out;
+ load repeat counter with 63;
+ take, deliver, notify bitfifo.out;
+ load repeat counter with 11;
+ take, deliver, notify bitfifo.out;
+
+// mux on second input
+lut3.inLut: literal 226;
+ [*] deliver;
+
+lut3.in1: literal 18683;
+ load repeat counter with 37; deliver;
+ literal 0;
+ load repeat counter with 37; deliver;
+
+lut3.in3: literal 12000;
+ load repeat counter with 37; deliver;
+ literal 0;
+ load repeat counter with 37; deliver;
+
+lut3.out: [*] wait, take, sendto alu3.in2;
+
+alu3.in1: literal 0; deliver; [*] take, deliver;
+alu3.in2: notify lut3.out; [*] take, deliver, notify lut3.out;
+alu3.in3: literal 0; deliver; [*] take, deliver;
+alu3.outBits: [*] take, sendto debug.in;
+
+alu3.out1: [*] take, sendto alu3.in1;
+alu3.out2: [*] take, sendto alu3.in3;
+
debug.in: [*] take, deliver;
projects / fleet.git / blobdiff