== FPGA ==============================================================
- reg [(`DATAWIDTH-1):0] temp;
- reg [(`DATAWIDTH):0] out_d;
+ reg [(`WORDWIDTH-1):0] temp;
+ reg [(`WORDWIDTH):0] out_d;
reg [1:0] state;
initial state = 0;
assign out_d_ = out_d;
- wire [(`DATAWIDTH-1):0] majority;
- wire [(`DATAWIDTH-1):0] xors;
+ wire [(`WORDWIDTH-1):0] majority;
+ wire [(`WORDWIDTH-1):0] xors;
genvar i;
generate
- for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
+ for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
assign majority[i] = (temp[i] & out_d[i]) | (in_d[i] & out_d[i]) | (temp[i] & in_d[i]);
assign xors[i] = temp[i] ^ out_d[i] ^ in_d[i];
end
end else if (state == 1) begin
temp <= in_d;
end else if (state == 2) begin
- out_d <= { majority[`DATAWIDTH-1:0], 1'b0 };
+ out_d <= { majority[`WORDWIDTH-1:0], 1'b0 };
temp <= xors;
`fill_out
end