== FPGA ==============================================================
- // FIXME
-/*
- reg have_a;
- reg [(`DATAWIDTH-1):0] reg_a;
- reg have_b;
- reg [(`DATAWIDTH-1):0] reg_b;
- reg have_op;
- reg [(`DATAWIDTH-1):0] reg_op;
+ reg have_in1;
+ reg [(`DATAWIDTH-1):0] reg_in1;
+ reg have_in2;
+ reg [(`DATAWIDTH-1):0] reg_in2;
+ reg have_in;
+ reg [(`PACKET_WIDTH-1):0] reg_in;
+ reg have_out1;
+ reg have_out2;
+ reg fire;
always @(posedge clk) begin
- if (!have_a) begin
- `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
+ if (!have_in1) begin
+ `onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
end
- if (!have_b) begin
- `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
+ if (!have_in2) begin
+ `onread(in2_r, in2_a) have_in2 = 1; reg_in2 = in2_d; end
end
- if (!have_op) begin
- `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
+ if (!have_in) begin
+ `onread(in_r, in_a) have_in = 1; reg_in = in_d; end
end
-
- if (have_a && have_b && have_op) begin
- case (reg_op)
- 0: out_d = reg_a + reg_b;
- 1: out_d = reg_a - reg_b;
- default: out_d = 0;
- endcase
- `onwrite(out_r, out_a)
- have_a = 0;
- have_b = 0;
- have_op = 0;
+
+ if (have_out1) begin
+ `onwrite(out1_r, out1_d) have_out1 = 0; end
+ end
+ if (have_out2) begin
+ `onwrite(out2_r, out2_d) have_out2 = 0; end
+ end
+
+ if (have_in && !have_out1 && !have_out2) begin
+ case (reg_in[`PACKET_WIDTH-1:`DATAWIDTH])
+ 00: /* in.swapIfZero */ fire = reg_in[`DATAWIDTH-1:0] == 0;
+ 06: /* in.muxIfZero */ fire = reg_in[`DATAWIDTH-1:0] == 0;
+ 12: /* in.deMuxIfZero */ fire = reg_in[`DATAWIDTH-1:0] == 0;
+ 01: /* in.swapIfNonZero */ fire = reg_in[`DATAWIDTH-1:0] != 0;
+ 07: /* in.muxIfNonZero */ fire = reg_in[`DATAWIDTH-1:0] != 0;
+ 13: /* in.deMuxIfNonZero */ fire = reg_in[`DATAWIDTH-1:0] != 0;
+ 02: /* in.swapIfNegative */ fire = reg_in[`DATAWIDTH-1:0] < 0;
+ 08: /* in.muxIfNegative */ fire = reg_in[`DATAWIDTH-1:0] < 0;
+ 14: /* in.deMuxIfNegative */ fire = reg_in[`DATAWIDTH-1:0] < 0;
+ 03: /* in.swapIfPositive */ fire = reg_in[`DATAWIDTH-1:0] > 0;
+ 09: /* in.muxIfPositive */ fire = reg_in[`DATAWIDTH-1:0] > 0;
+ 15: /* in.deMuxIfPositive */ fire = reg_in[`DATAWIDTH-1:0] > 0;
+ 04: /* in.swapIfNonNegative */ fire = reg_in[`DATAWIDTH-1:0] >= 0;
+ 16: /* in.deMuxIfNonNegative */ fire = reg_in[`DATAWIDTH-1:0] >= 0;
+ 10: /* in.muxIfNonNegative */ fire = reg_in[`DATAWIDTH-1:0] >= 0;
+ 05: /* in.swapIfNonPositive */ fire = reg_in[`DATAWIDTH-1:0] <= 0;
+ 11: /* in.muxIfNonPositive */ fire = reg_in[`DATAWIDTH-1:0] <= 0;
+ 17: /* in.deMuxIfNonPositive */ fire = reg_in[`DATAWIDTH-1:0] <= 0;
+ endcase
+
+ if (reg_in[`PACKET_WIDTH-1:`DATAWIDTH] <= 5) begin
+ if (have_in1 && have_in2) begin
+ have_out1 = 1;
+ have_out2 = 1;
+ have_in1 = 0;
+ have_in2 = 0;
+ out1_d = fire ? reg_in2 : reg_in1;
+ out2_d = fire ? reg_in1 : reg_in2;
+ end
+ end else if (reg_in[`PACKET_WIDTH-1:`DATAWIDTH] <= 11) begin
+ if (fire && have_in2) begin
+ have_out1 = 1;
+ have_in2 = 0;
+ out1_d = in2_d;
+ end else if (!fire && have_in1) begin
+ have_out1 = 1;
+ have_in1 = 0;
+ out1_d = in1_d;
+ end
+ end else begin
+ if (have_in1) begin
+ if (fire) begin
+ have_out2 = 1;
+ out2_d = in1_d;
+ have_in1 = 0;
+ end else begin
+ have_out1 = 1;
+ out1_d = in1_d;
+ have_in1 = 0;
+ end
+ end
end
- end
+ end
end
-*/