== FPGA ==============================================================
- reg [`DATAWIDTH-1:0] temp;
- initial temp = {`DATAWIDTH{1'b1}};
+ reg [`WORDWIDTH-1:0] temp;
+ initial temp = {`WORDWIDTH{1'b1}};
reg full;
initial full = 0;
wire op_count; assign op_count = inOp_d==12;
end else if (`inOp_full) begin
if (!full) begin
if (op_count && `in1_full && `in2_full) begin
- temp <= in1_d[`DATAWIDTH-1:0] - in2_d[`DATAWIDTH-1:0];
+ temp <= in1_d[`WORDWIDTH-1:0] - in2_d[`WORDWIDTH-1:0];
`drain_in1
full <= 1;
end else if (op_c1 && `in1_full) begin
- temp <= in1_d[`DATAWIDTH-1:0]-1;
+ temp <= in1_d[`WORDWIDTH-1:0]-1;
`drain_in1
full <= 1;
end else if (op_c2 && `in2_full) begin
- temp <= in2_d[`DATAWIDTH-1:0]-1;
+ temp <= in2_d[`WORDWIDTH-1:0]-1;
`drain_in2
full <= 1;
end
- end else if (temp[`DATAWIDTH-1]) begin
+ end else if (temp[`WORDWIDTH-1]) begin
full <= 0;
`drain_inOp
if (op_count) begin