== FPGA ==============================================================
+ wire [3:0] inOp_d_trunc;
+ assign inOp_d_trunc = inOp_d[3:0];
+
reg [`WORDWIDTH-1:0] temp;
initial temp = {`WORDWIDTH{1'b1}};
reg full;
initial full = 0;
- wire op_count; assign op_count = inOp_d==12;
+ wire op_count; assign op_count = inOp_d_trunc==12;
wire op_repeat; assign op_repeat = inOp_d[3:2]==0;
wire op_pass; assign op_pass = inOp_d[3:2]==1;
wire op_drop; assign op_drop = inOp_d[3:2]==2;