adjust ships to use fill/drain/full/empty macros

[fleet.git] / ships / DDR2.ship

diff --git a/ships/DDR2.ship b/ships/DDR2.ship
deleted file mode 100644 (file)
index b594c87..0000000
--- a/ships/DDR2.ship
+++ /dev/null
@@ -1,79 +0,0 @@
-ship: DDR2
-
-== Ports ===========================================================
-data  in:    inAddrRead
-data  in:    inAddrWrite
-data  in:    inDataWrite
-
-data  out:   out
-
-== TeX ==============================================================
-
-== Fleeterpreter ====================================================
-    public void service() { }
-== FleetSim ==============================================================
-
-== FPGA ==============================================================
-
-  reg         ddr2_addr_r;
-  reg         ddr2_isread;
-  reg         ddr2_write_data_push;
-  reg         ddr2_read_data_pop;
-  reg  [`DATAWIDTH:0]  out_d;
-
-  assign ddr2_addr_r_ = ddr2_addr_r;
-  assign ddr2_isread_ = ddr2_isread;
-  assign ddr2_addr_ = !ddr2_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
-  assign ddr2_write_data_push_ = ddr2_write_data_push;
-  assign ddr2_read_data_pop_ = ddr2_read_data_pop;
-  assign ddr2_write_data_ = { inDataWrite_d[31:5], inDataWrite_d[4], inDataWrite_d[35:0] };
-//  assign ddr2_write_data_ = inDataWrite_d[(`DATAWIDTH-1):0];
-  assign out_d_ = out_d;
-
-  always @(posedge clk) begin
-
-    if (!rst) begin
-      `reset
-      ddr2_isread <= 0;
-      ddr2_addr_r <= 0;
-      ddr2_read_data_pop <= 0;
-
-    end else begin
-      `flush
-
-      if (!inAddrRead_r_  && inAddrRead_a)  inAddrRead_a  <= 0;
-      if (!inDataWrite_r_ && inDataWrite_a) inDataWrite_a <= 0;
-      if (!inAddrWrite_r_ && inAddrWrite_a) inAddrWrite_a <= 0;
-      if ( out_r          && out_a)         out_r <= 0;
-
-      if (ddr2_addr_r && !ddr2_addr_a) begin
-         // busy
-      end else if (ddr2_addr_r &&  ddr2_addr_a && !ddr2_isread) begin
-          ddr2_addr_r <= 0;
-          inAddrWrite_a <= 1;
-          inDataWrite_a <= 1;
-          out_d <= { 1'b1, 37'b0 };
-          out_r <= 1;
-      end else if (ddr2_addr_r &&  ddr2_addr_a && ddr2_isread) begin
-          ddr2_addr_r <= 0;
-          inAddrRead_a <= 1;
-          out_d <= { 1'b0, ddr2_read_data[36:0] };
-          out_r <= 1;
-      end else if (!out_r && !out_a && inAddrWrite_r && !inAddrWrite_a && inDataWrite_r && !inDataWrite_a && !ddr2_addr_r && !ddr2_addr_a) begin
-          ddr2_addr_r <= 1;
-          ddr2_isread <= 0;
-      end else if (!out_r && !out_a && inAddrRead_r && !inAddrRead_a && !ddr2_addr_r && !ddr2_addr_a) begin
-          ddr2_addr_r <= 1;
-          ddr2_isread <= 1;
-      end
-    end
-  end
-
-
-== Test ========================================================
-#skip
-
-== Constants ========================================================
-
-== Contributors =========================================================
-Adam Megacz <megacz@cs.berkeley.edu>