reg dram_isread;
reg dram_write_data_push;
reg dram_read_data_pop;
- reg [`DATAWIDTH:0] out_d;
+ reg [`WORDWIDTH:0] out_d;
wire [31:0] dram_addr__;
assign dram_addr_r_ = dram_addr_r;
assign dram_write_data_push_ = dram_write_data_push;
assign dram_read_data_pop_ = dram_read_data_pop;
assign dram_write_data_ = inDataWrite_d;
-// assign dram_write_data_ = inDataWrite_d[(`DATAWIDTH-1):0];
+// assign dram_write_data_ = inDataWrite_d[(`WORDWIDTH-1):0];
assign out_d_ = out_d;
always @(posedge clk) begin