implement port percolation

[fleet.git] / ships / DRAM.ship

diff --git a/ships/DRAM.ship b/ships/DRAM.ship
index e3bdbb6..322c3c1 100644 (file)
--- a/ships/DRAM.ship
+++ b/ships/DRAM.ship
@@ -7,17 +7,18 @@ data  in:    inDataWrite
 
 data  out:   out
 
-percolate up:     dram_addr_                32
-percolate up:     dram_addr_r_              1
-percolate down:   dram_addr_a               1
-percolate up:     dram_isread_              1
-percolate up:     dram_write_data_          64
-percolate up:     dram_write_data_push_     1
-percolate down:   dram_write_data_full      1
-percolate down:   dram_read_data            64
-percolate up:     dram_read_data_pop_       1
-percolate down:   dram_read_data_empty      1
-percolate down:   dram_read_data_latency    2
+percolate up:            ddr1_Clk_pin       1
+percolate up:            ddr1_Clk_n_pin     1
+percolate up:            ddr1_Addr_pin      13
+percolate up:            ddr1_BankAddr_pin  2
+percolate up:            ddr1_CAS_n_pin     1
+percolate up:            ddr1_CE_pin        1
+percolate up:            ddr1_CS_n_pin      1
+percolate up:            ddr1_RAS_n_pin     1
+percolate up:            ddr1_WE_n_pin      1
+percolate up:            ddr1_DM_pin        4
+percolate inout:         ddr1_DQS           4
+percolate inout:         ddr1_DQ            32
 
 == TeX ==============================================================
 
@@ -27,6 +28,18 @@ percolate down:   dram_read_data_latency    2
 
 == FPGA ==============================================================
 
+  wire  [31:0]  dram_addr;
+  wire          dram_addr_r_;
+  wire          dram_addr_a;
+  wire          dram_isread_;
+  wire  [63:0]  dram_write_data_;
+  wire          dram_write_data_push_;
+  wire          dram_write_data_full;
+  wire   [63:0] dram_read_data;
+  wire          dram_read_data_pop_;
+  wire          dram_read_data_empty;
+  wire   [1:0]  dram_read_data_latency;
+
   reg         dram_addr_r;
   reg         dram_isread;
   reg         dram_write_data_push;
@@ -41,9 +54,42 @@ percolate down:   dram_read_data_latency    2
   assign dram_write_data_push_ = dram_write_data_push;
   assign dram_read_data_pop_ = dram_read_data_pop;
   assign dram_write_data_ = inDataWrite_d;
-//  assign dram_write_data_ = inDataWrite_d[(`WORDWIDTH-1):0];
   assign out_d_ = out_d;
 
+   ddr_ctrl 
+   #(
+       .clk_freq( 50000000 ),
+       .clk_multiply( 12 ),
+       .clk_divide( 5 ),
+       .phase_shift( 0 ),
+       .wait200_init( 26 )
+   ) ddr_ctrl (
+          .ddr_a( ddr1_Addr_pin ),
+          .ddr_clk( ddr1_Clk_pin ),
+          .ddr_clk_n( ddr1_Clk_n_pin ),
+          .ddr_ba( ddr1_BankAddr_pin ),
+          .ddr_dq( ddr1_DQ ),
+          .ddr_dm( ddr1_DM_pin ),
+          .ddr_dqs( ddr1_DQS ),
+          .ddr_cs_n( ddr1_CS_n_pin ),
+          .ddr_ras_n( ddr1_RAS_n_pin ),
+          .ddr_cas_n( ddr1_CAS_n_pin ),
+          .ddr_we_n( ddr1_WE_n_pin ),
+          .ddr_cke( ddr1_CE_pin ),
+   
+          .clk(clk),
+          .reset(!sys_rst_pin),
+          .rot(3'b100),
+   
+          .fml_wr(!dram_isread && dram_addr_r),
+          .fml_done(dram_addr_a),
+          .fml_rd( dram_isread && dram_addr_r),
+          .fml_adr(dram_addr),
+          .fml_din(dram_write_data),
+          .fml_dout(dram_read_data),
+          .fml_msk(16'h0)
+   );
+
   always @(posedge clk) begin
 
     if (!rst) begin