== FPGA ==============================================================
wire [31:0] dram_addr;
- wire dram_addr_r_;
+ wire [31:0] dram_addr__;
+
wire dram_addr_a;
- wire dram_isread_;
- wire [63:0] dram_write_data_;
- wire dram_write_data_push_;
- wire dram_write_data_full;
- wire [63:0] dram_read_data;
- wire dram_read_data_pop_;
- wire dram_read_data_empty;
- wire [1:0] dram_read_data_latency;
-
- reg dram_addr_r;
- reg dram_isread;
- reg dram_write_data_push;
- reg dram_read_data_pop;
+ wire [63:0] dram_write_data;
+ wire [63:0] dram_read_data;
+
+ reg dram_addr_r;
+ reg dram_isread;
+
+ assign dram_addr__ = dram_isread ? inAddrRead_d[31:0] : inAddrWrite_d[31:0];
+ assign dram_addr = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
+
reg [`WORDWIDTH:0] out_d;
- wire [31:0] dram_addr__;
-
- assign dram_addr_r_ = dram_addr_r;
- assign dram_isread_ = dram_isread;
- assign dram_addr__ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
- assign dram_addr_ = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
- assign dram_write_data_push_ = dram_write_data_push;
- assign dram_read_data_pop_ = dram_read_data_pop;
- assign dram_write_data_ = inDataWrite_d;
assign out_d_ = out_d;
ddr_ctrl
.ddr_cke( ddr1_CE_pin ),
.clk(clk),
- .reset(!sys_rst_pin),
+ .reset(rst),
.rot(3'b100),
.fml_wr(!dram_isread && dram_addr_r),
always @(posedge clk) begin
- if (!rst) begin
+ if (rst) begin
`reset
dram_isread <= 0;
dram_addr_r <= 0;
- dram_read_data_pop <= 0;
end else begin
- `flush
`cleanup
if (dram_addr_r && !dram_addr_a) begin
== Test ========================================================
#skip
+// expected output
+#expect 10
+
+// ships required in order to run this code
+#ship debug : Debug
+#ship memory : DRAM
+
+memory.inAddrWrite:
+ set word=0;
+ deliver;
+ deliver;
+
+memory.inDataWrite:
+ set word=-1;
+ deliver;
+ set word=-1;
+ deliver;
+
+memory.inAddrRead:
+ recv token;
+ set word=0;
+ deliver;
+
+memory.out:
+ collect;
+ collect;
+ send token to memory.inAddrRead;
+ collect;
+ send to debug.in;
+
+debug.in:
+ set ilc=*;
+ recv, deliver;
+
== Constants ========================================================