.ddr_cke( ddr1_CE_pin ),
.clk(clk),
- .reset(!rst),
+ .reset(rst),
.rot(3'b100),
.fml_wr(!dram_isread && dram_addr_r),
always @(posedge clk) begin
- if (!rst) begin
+ if (rst) begin
`reset
dram_isread <= 0;
dram_addr_r <= 0;
end else begin
- `flush
`cleanup
if (dram_addr_r && !dram_addr_a) begin