== FPGA ==============================================================
- // FIXME: use the other chip (64-bit data bus)
-
reg dram_addr_r;
reg dram_isread;
reg dram_write_data_push;
reg dram_read_data_pop;
- reg [`DATAWIDTH-1:0] out_d;
+ reg [`DATAWIDTH:0] out_d;
+ wire [31:0] dram_addr__;
assign dram_addr_r_ = dram_addr_r;
assign dram_isread_ = dram_isread;
- assign dram_addr_ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
+ assign dram_addr__ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
+ assign dram_addr_ = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
assign dram_write_data_push_ = dram_write_data_push;
assign dram_read_data_pop_ = dram_read_data_pop;
- assign dram_write_data_ = inDataWrite_d[31:0];
+ assign dram_write_data_ = inDataWrite_d;
+// assign dram_write_data_ = inDataWrite_d[(`DATAWIDTH-1):0];
assign out_d_ = out_d;
always @(posedge clk) begin
dram_read_data_pop <= 0;
end else begin
+ `flush
- if (!inAddrRead_r && inAddrRead_a) inAddrRead_a <= 0;
- if (!inDataWrite_r && inDataWrite_a) inDataWrite_a <= 0;
- if (!inAddrWrite_r && inAddrWrite_a) inAddrWrite_a <= 0;
- if ( out_r && out_a) out_r <= 0;
+ if (!inAddrRead_r_ && inAddrRead_a) inAddrRead_a <= 0;
+ if (!inDataWrite_r_ && inDataWrite_a) inDataWrite_a <= 0;
+ if (!inAddrWrite_r_ && inAddrWrite_a) inAddrWrite_a <= 0;
+ if ( out_r && out_a) out_r <= 0;
if (dram_addr_r && !dram_addr_a) begin
// busy
dram_addr_r <= 0;
inAddrWrite_a <= 1;
inDataWrite_a <= 1;
+ out_d <= { 1'b1, 37'b0 };
+ out_r <= 1;
end else if (dram_addr_r && dram_addr_a && dram_isread) begin
dram_addr_r <= 0;
inAddrRead_a <= 1;
- out_d <= dram_read_data;
+ out_d <= { 1'b0, dram_read_data[36:0] };
out_r <= 1;
- end else if (inAddrWrite_r && !inAddrWrite_a && inDataWrite_r && !inDataWrite_a && !dram_addr_r && !dram_addr_a) begin
+ end else if (!out_r && !out_a && inAddrWrite_r && !inAddrWrite_a && inDataWrite_r && !inDataWrite_a && !dram_addr_r && !dram_addr_a) begin
dram_addr_r <= 1;
dram_isread <= 0;
- end else if (inAddrRead_r && !inAddrRead_a && !out_r && !out_a && !dram_addr_r && !dram_addr_a) begin
+ end else if (!out_r && !out_a && inAddrRead_r && !inAddrRead_a && !dram_addr_r && !dram_addr_a) begin
dram_addr_r <= 1;
dram_isread <= 1;
end