wire break;
wire uart_cts;
assign uart_cts = 0;
- assign rst_out = rst_in || (force_reset!=0) || break;
+ assign rst_out = rst_in || (force_reset!=0) /* || break */;
// fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
// using a 33Mhz clock,
// fpga -> host
always @(posedge clk) begin
- if (rst_in || break) begin
+ if (rst_in /* || break */) begin
count_in <= 0;
count_out <= 0;
force_reset <= 0;