percolate down: clk_pin 1
percolate up: clk_out 1
+percolate up: gpio_led_c 1
+percolate up: gpio_led_e 1
+percolate up: gpio_led_n 1
+percolate up: gpio_led_s 1
+percolate up: gpio_led_w 1
+percolate down: gpio_dip_sw1 1
+
+
== TeX ==============================================================
This ship is used for debugging. It has only one port, {\tt in}.
== FPGA:ML509 ==============================================================
+ assign gpio_led_n = 0;
+ assign gpio_led_s = 0;
+ assign gpio_led_e = 1;
+ assign gpio_led_w = 1;
+
+ wire tdo;
+ wire update;
+ wire shift;
+ wire reset;
+ wire tdi;
+ wire sel;
+ wire drck;
+ BSCAN_VIRTEX5
+ #(.JTAG_CHAIN(1))
+ bscanvirtex(.TDO(tdo),
+ .UPDATE(update),
+ .SHIFT(shift),
+ .RESET(reset),
+ .TDI(tdi),
+ .SEL(sel),
+ .DRCK(drck));
+
+ wire [9:0] din;
+ wire [9:0] dout;
+ reg [9:0] dout_r;
+ wire strobe_o;
+ assign din = 10'h71;
+ wire ack_i;
+ assign ack_i = 1;
+
+ fjmem_core
+ my_fjmem_core(
+ .clkdr_i (drck),
+ .trst_i (reset),
+ .shift_i (shift),
+ .update_i (update),
+ .tdi_i (tdi),
+ .tdo_o (tdo),
+ .clk_i (clk),
+ .res_i (rst),
+
+ .strobe_o (strobe_o),
+ .read_o (),
+ .write_o (write_o),
+ .ack_i (ack_i),
+ .cs_o (),
+ .addr_o (),
+ .din_i (dout_r),
+ .dout_o (dout)
+ );
+
+ always @(posedge clk) begin
+ if (strobe_o)
+ dout_r <= dout;
+ end
+
+
wire break_i;
reg send_k;
initial send_k = 0;
Net uart_out TIG;
Net uart_out PULLUP;
-
+NET gpio_led_c LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET gpio_led_e LOC="AG23"; # Bank 2, Vcco=3.3V
+NET gpio_led_n LOC="AF13"; # Bank 2, Vcco=3.3V
+NET gpio_led_s LOC="AG12"; # Bank 2, Vcco=3.3V
+NET gpio_led_w LOC="AF23"; # Bank 2, Vcco=3.3V
+NET gpio_dip_sw1 LOC="U25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
== Test ================================================================