cleanup, add Generator for verilog netlists

[fleet.git] / ships / Debug.ship

diff --git a/ships/Debug.ship b/ships/Debug.ship
index aaeff49..7978ba3 100644 (file)
--- a/ships/Debug.ship
+++ b/ships/Debug.ship
@@ -1,19 +1,28 @@
 ship: Debug
 
 == Ports ===========================================================
-data  in:   data
+data  in:   in
 
 == Constants ========================================================
 
 == TeX ==============================================================
+\begin{verbatim}
+
+TODO: have some way to log multiple separate streams; use sibling
+      ports to deliver an opcode
+
+TODO: have a way to programmatically read back the output of the debug
+      ship?
+
+\end{verbatim}
 
 == Fleeterpreter ====================================================
 public void service() {
-  if (box_data.dataReadyForShip())
-    ((Interpreter)getFleet()).debug(box_data.removeDataForShip());
+  if (box_in.dataReadyForShip())
+    ((Interpreter)getFleet()).debug(box_in.removeDataForShip());
 }
 
-== ArchSim ==============================================================
+== FleetSim ==============================================================
 
 == FPGA ==============================================================
 `include "macros.v"